Network-on-Chip

Circuit-Switched NoCs | Crossbars | NoC Concept | Packet-Switched NoCs | Sockets, Interfaces and Reuse | Wiring Problem

Circuit-Switched NoCs

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A Case Study in Networks-on-Chip Design for Embedded Video  J. Xu, W. Wolf, J. Henkel, S. Chakradhar  DATE, 2004  Proceedings, DATE 2004; Volume 2  February 16-20, 2004  770-775 
A flexible circuit switched NOC for FPGA based sytems  C. Hilton, B. Nelson  FPL    2005  24-26 
An architecture and compiler for scalable on-chip communication  J. Liang    IEEE Trans. VLSI Syst.; Vol. 12, Issue 7  2004  711-726 
An Energy-Efficient Reconfigurable Circuit-Switched Network-on-Chip  P.T. Wolkotte, G.J.M. Smit, G.K. Rauwerda, L.T. Smit  Proceedings of IEEE International Parallel and Distributed Processing Symposium (IPDPS)    04-08 April 2005  pp. 155a - 155a 
An energy-efficient reconfigurable circuit-switched network-on-chip  P. Wolkotte, et al.    IPDPS  Apr. 2005  155a 
Cost-Performance Trade-offs in Networks-on-Chip: A Simulation-Based Approach  S.G. Pestana, E. Rijpkema, A. Radulescu, K. Goossens, O.P. Gangwal  DATE, 2004  Proceedings, DATE 2004; Volume 2  February 16-20, 2004  764-769 
Design of a switching node (router) for on-chip networks  S. Sathe, D. Wiklund, D. Liu    ASIC  Oct. 2003  75-78 
On a design of crossroad switches for low-power on-chip communication architectures  J.-S. Chen, K.-C. Chang, T.-F. Chen    ISCAS  May 2006   
Spatial division multiplexing: a novel approach for guaranteed  A. Leroy, P. Marchal, A. Shickova, F. Catthoor, F. Robert, D. Verkest  CODES+ISSS05, Jersey City, New Jersey, USA    Sept. 1921, 2005  pp .81-86 
Switched interconnect for system-on-chip designs  D. Wiklund, D. Liu    IP2000  Oct. 2000  192-198 

NoC Concept

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3-d topologies for networks-on-chips  V. F. Pavlidis, E. G. Friedman    IEEE Trans. VLSI Syst.  2007   
A generic architecture for on-chip packet-switched interconnections  P. Guerrier, A. Greiner    DATE  Mar. 2000  250-256 
A network on chip architecture and design methodology  S. Kumar, A. Jantsch, J.-P. Soininen, M. Forsell, M. Millberg, J. berg, K. Tiensyrj, and A. Hemani  In Proceedings of IEEE Computer Society Annual Symposium on VLSI    April 2002   
A survey of research and practices of Network-on-chip  Tobias Bjerregaard, Shankar Mahadevan    ACM Computing Surveys; Volume 38, Issue 1, Article 1  2006  2006 
An Autonomous Error-tolerant Cell for Scalable Network-on-Chip Architectures  Valtonen, T., J. Isoaho, H. Tenhunen  In Proceedings Norchip    2001  pp. 198 - 203 
Coping with latency in SOC design  L.P. Carloni, A.L. Sangiovanni-Vincentelli  IEEE Micro  Volume 22, Issue 5  Sept-Oct. 2002  pp. 24 - 35 
Essential fault-tolerance metrics for NoC infrastructures, in IOLTS  C. Grecu, L. Anghel, P.P. Pande, A. Ivanov, and R. Saleh    Jul.2007    pp.37-42 
Extending platform-based design to network on chip systems  J.-P. Soininen, A. Jantsch, M. Forsell, A. Pelkonen, J. Kreku, S. Kumar    VLSI Design  Jan. 2003  401-408 
Interconnect-centric design for advanced SoC and NoC  J. Nurmi, H. Tenhunen, J. Isoaho, A. Jantsch    Doredrecht, The Netherlands: Kluwer Academic Publishers  2004   
Interconnect-Centric Design for Advanced SoC and NoC  Eds. J. Nurmi, H. Tenhunen, J. Isoaho, A. Jantsch    Kluwer Academic Publishers  2004   
Key research problems in NoC design: a holistic perspective  Umit Y. Ogras, Jingcao Hu, Radu Marculescu  CODES 2005    2005  pp. 69-75 
Network on chip: An architecture for billion transistor era  A. Hermani, A. Jantsch, S. Kumar, A. Postula, J. Oberg, M. Millberg, D. Lindqvist    Norchip  2000   
Networks on Chip  A. Jantsch and H. Tenhunen    Kluwer Academic Publishers  February 2003   
Networks on chips: a new SoC paradigm  Benini, L.; De Micheli, G    Volume: 35 Issue: 1  January 2002  pp. 70 -78 
Networks on Chips: From research to products  G. De Micheli, C. Seiculescu, S. Murali, L. Benini, F. Angiolini, A. Pullini  Design Automation Conference (DAC), 2010    2010  pp. 300 - 305 
Networks on chips: technology and tools  L. Benini, G. de Micheli    Morgan Kaufmann  2006   
Networks on silicon: blessing or nightmare?  P. Wielage, K. Goossens    DSD  Sep. 2002  196-200 
On-Chip Networks: A Scalable, Communication-Centric Embedded System Design Paradigm  J. Henkel, W. Wolf, S. Chakradhar  17th International Conference on VLSI Design  Proceedings, 17th International Conference on VLSI Design  January 5-9  845-851 
Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives, R. in IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (TCAD)  R. Marculescu, U. Y. Ogras, L.-S. Peh, N. E. Jerger, Y. Hoskote    Jan. 2009.    vol. 28, no. 1, pp. 3-21 
Research challenges for on-chip interconnection networks  J. Owens, et al.    IEEE Micro; Volume 27, Issue 5  Sep-Oct. 2007  96-108 
Route Packets, Not Wires: on-chip Interconnection Networks  W.J. Dally, B. Towles  Design Automation Conference (DAC), 2001  Proceedings, DAC 2001  2001  684 
Survey of Network-on-chip Proposals  E. Salminen, A. Kulmala, T. Hamalainen    www.ocpip.org/socket/whitepapers  April 9, 2008  13 pages 
Testing network-on-chip communication fabrics  C. Grecu, A. Ivanov, R. Saleh, P. Pande    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems; Volume 26, No. 10  Dec. 2007  2201-2014 
Towards on-chip fault-tolerant communication  T. Dumitras, S. Kerner, R. Marculescu  ASP/DAC, 2003  Proceedings, ASP/DAC 2003  January 21-24, 2003  225 - 232 
Towards open network-on-chip benchmarks  C. Grecu, P. Pande, A. Ivanov, R. Marculescu, E. Salminen, A. Jantsch    NOCS  May 2007  205 

Packet-Switched NoCs

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A .13 um 1Gb/s/channel store-and-forward network-on-chip  F. Mondinelli, M. Borgatti, Z. Vajna  SOCC    Sep. 2004  141-142 
A 51mW 1.6 GHz on-chip network forlow-powerheterogeneous SoC platform  K. Lee, S.-J. Lee, S.-E. Kim, H.-M. Choi, D. Kim, S. Kim, M.-W. Lee, and H.-J. Yoo  ISSCC,Feb.2004    Feb.2004  pp.152-158 
A High-Performance Router Design for VDSM NoCs  A. Narasimhan, K. Srinivasan, R. Sridhar  IEEE International SOC Conference    Sept. 25-28, 2005  pp. 301 - 304. 
A High-Speed and Lightweight On-Chip Crossbar Switch Scheduler for On-Chip Interconnection Networks  Kangmin Lee, Se-Joong Lee, Hoi-Jun Yoo  IEEE ESSCIRC 2004  Digest of Technical Papers, ESSCIRC 2003  Sept. 16-18, 2003  Pages: 453-456 
A high-throughput network-on-chip architecture for systems-on-chip interconnects  A. Bouhraoua, M.E. Elrabaa    Int'l Symposium on Soc  Nov. 2006  127-130 
A low latency router supporting adaptivity for on-chip interconnects  J. Kim, et al.  DAC    Jun. 2005  559-564 
A multi-path routing strategy with guaranteed in-order packet delivery and fault-tolerance for networks on chip  S. Murali, D. Atienza, L. Benini, G. De Micheli  Design Automation Conference (DAC), 2006    2006  pp. 845 – 848 
A reconfigurable baseband platform based on an asynchronous network-on-chip  D. Lattard, et al.    IEEE J. Solid-State Circuits; Volume 43, Issue 1  223-235   
A Router Architecture for Connection-Oriented Service Guarantees in the MANGO Clockless Network-  T. Bjerregaard and J. Sparsoe  DATE 2005    March 7-11, 2005  Vol.2 , pp. 1226-1231 
A Scalable Embedded On-Chip Multiprocessor Architecture for Network Applications  J. Niemann, C. Puttmann, M. Porrmann, U. Rückert    Lecture Notes in Computer Science, Volume 3894  Feb 2006  268 - 282 
A validation and performance evaluation tool for ProtoNoc  D. Castells-Rufas, J. Joven, J. Carrabina    Int'l Symposium on Soc  Nov. 2006  159-162 
A virtual channel network-on-chip for GT and BE traffic      ISVLSI; Vol 00  Mar. 2006   
An 80-tile Sub-100-W TeraFLOPS processor in 65-nm CMOS  S. Vangal, et al.    IEEE J. Solid-State Circuits; Volume 43, Issue 1  Jan. 2007  29-41 
An 81.6 GOPS object recognition processor based on noc and visual image processing memory  D. Kim, M. Kim, J.-Y. Kim, S. Lee, H.-J. Yoo      CICC   
An Asynchronous NOC Architecture Providing Low Latency Service and Its Multi-Level Design Framework  E. Beigne, F. Clermidy, P. Vivet, A. Clouard, M. Renaudin  Proceedings of 11th IEEE International Symposium on Asynchronous Circuits and Systems    4-16 March 2005  pp. 54 - 63 
An asynchronous on-chip network router with quality-of-service (qos) support  F. Felicijan and S. Furber  SOCC    Sep. 2004  pp. 274277 
An Asynchronous Router for Multiple Service Levels Networks on Chip  D. Rostislav, V. Vishnyakov, E. Friedman, Ran Ginosar  Proceedings of IEEE International Symposium on Asynchronous Circuits and Systems(ASYNC)    14-16 March 2005  pp. 224-229 
An efficient on-chip NI offering guaranteed services, shared-memory abstraction, and flexible networ  A. Radulescu, et al.    IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems; Vol. 21, Issue 1  Jan. 2005  4-17 
An interconnect architecture for networking systems on chips  F. Karim, A. Nguyen, S. Dey    IEEE Micro; Vol 22, Issue 5  Sep.-Oct. 2002  36-45 
Applying cdma technique to network-on-chip  Xin Wang, T. Ahonen, J. Nurmi    IEEE Trans. VLSI Syst. Volume 15, Issue 10    1091-1100 
Architecture of a dynamically reconfigurable noc for adaptive reconfigurable mpsoc  B. Ahmad, A. Erdogan, and S. Khawam  AHS    Jun. 2006  pp. 405411 
BLACK-BUS: A New Data-Transfer Technique Using Local Address on Networks-on-Chip  K. Anjo, Y. Yamada, M. Koibuchi, A. Jouraku, H. Amano  18th IPDPS 2004  Proceedings, 18th IPDPS  April 26-30 2004  10-17 
Bringing NoCs to 65nm  A. Pullini,F. Angiolini,S. Murali D. Atienza, G. De Micheli, and L. Benini    Sep.-Oct 2007    IEEE Micro, vol.27, no.5, pp.75-85 
Buffer Implementation for Proteo Network-on-chip  I. Saastamoinen, M. Alho, J. Nurmi  ISCAS, 2003  Proceedings, ISCAS 2003 Volume: 2  May 25-28, 2003  II-113 - II-116 
Communication architecture optimization: making the shortest path shorter in regular networks-on-chi  U. Ogras, et al.    DATE  Mar. 2006   
Design and implementation of a routing switch for on-chip interconnection networks  K.-C. Chang, J.-S. Shen, T.-F. Chen    AP-ASIC  Aug. 2004  392-395 
Design of a Switch for Network on Chip Applications  P.P. Pande, C. Grecu, A. Ivanov, Res Saleh  IEEE ISCAS, 2003  ISCAS 2003 Volume: V  2003  217-220 
Designing message-dependent deadlock free net works on chips for application-specific systems-on-chips, in IFIP  S. Murali,P. Meloni,F. Angiolini,D. Atienza, S. Carta,L. Benini,L. Raffo, andG.deMicheli      2006   
DyAD - smart routing for networks-on-chip  J. Hu, R. Marculescu  DAC    Jun. 2004  260-263 
Guaranteed Bandwidth Using Looped Containers in Temporally Disjoint Networks Within the Nostrum NoCs  M. Millberg, E. Nilsson, R. Thid, A. jansch  DATE, 2004  Proceedings, DATE 2004; Volume 2  February 16-20, 2004  890-895 
Hermes project web page  A.V. de Mello, L.H. Moller    http://toledo.inf.pucrs.br/gaph/Projects/Hermes/Hermes.html  2004   
Hermes: an infrastructure for low area overhead packet-switching networks on chip  F. Moraes, et al.    Integration, the VLSI Journal; Vol. 38, Issue 1  Oct. 2004  69-93 
Hierarchical Graph: A New Cost Effective Architecture for Network on Chip  A. Vahdatpour, A. Tavakoli, M. Falaki    Lecture Notes in Computer Science, Volume 3824,  Nov 2005  Pages 311 - 320 
Highly Scalable Network on Chip for Reconfigurable Systems  T.A. Bartic, J-Y. Mignolet, V. Nollet, T. Marescaux, D. Verkest, S. Vernalde, R. Lauwereins  International Symposium on System-on-Chip, 2003  Proceedings, International Symposium on System-on-Chip, 2003  November 2003  79 - 82 
Integrated Modeling and Generation of a Reconfigurable Network-on-Chip  D. Ching, P. Schaumont, I. Verbauwhede  18th IPDPS 2004  Proceedings, 18th IPDPS  April 26-30 2004  139-145 
Integration of a NOC-based multimedia processing platform  B. Ahmad, A. Erdogan, S. Khawam    FPL  Aug. 2005  606-611 
Interfacing Cores with On-chip Packet-Switched Networks  P. Bhojwani, R. Mahapatra  Proceedings, IEEE VLSI Design  January 4-8, 2003  382 - 387  382 - 387 
Interfacing cores with on-chip packet-switched networks  P. Bhojwani, R. Mahapatra    VLSI Design  Jan. 2003  382-387 
Issues in the development of a practical NoC: the Proteo concept  D. Siguenza-Tortosa, T. Ahonen, J. Nurmi    Integration, the VLSI Journal, Vol. 38, Issue 1  Oct. 2004  95-105 
Low-power network-on-chip for high-performance soc design  K. Lee, S.-J. Lee, H.-J. Yoo    IEEE Trans. VLSI Syst.; Vol 14, Issue 2  Feb. 2006  148-160 
Micro-network for SoC: Implementation of a 32-port SPIN network  A. Andriahantenaina, A. Greiner    DATE  Mar. 2003  1128-1129 
MoCSYS: A Multi-Clock Hybrid Two-Layer Router Architecture and Integrated Topology Synthesis Framewo      VLSI Design  2008  397-402 
MultiNoC: A Multiprocessing System Enabled by a Network on Chip  A. Mello, L. Moller, N. Calazans, F.Moraes  Proceedings of Design, Automation and Test in Europe (DATE)    07-11 March 2005  pp. 234 - 23 
Network-on-chip architectures and design methods  L. Benini, D. Bertozzi  IEEE Proceedings on Computers and Digital Techniques  Volume 152, Issue 2  March 2005  pp. 261 - 272 
Network-on-chip for reconfigurable systems: From high-level design down to implementation  T. Bartic  FPL    2004  637-647 
On-Chip Network Based Embedded Core Testing  Jong-Sun Kim, Min-Su Hwang, Seungsu Roh, Ja-Young Lee, Kangmin Lee, Se-Joong Lee, Hoi-Jun Yoo  IEEE International SoC Conference (SOCC) 2004  Digest of Technical Papers, SOCC 2004  Sept. 12-15, 2004  Pages: 223-226 
On-line reconfigurable extended generalized fat tree network-on-chip for multiprocessor soc circuits  H. Kariniemi  Tampere University of Technology Ph.D dissertation    Sep. 2006   
Panacea - a case study on the panacea noc - a nostrum network on chip prototype  E. Nilsson, J. Oberg    Royal Institute of Technology, Tech. Rep. 229  Apr. 2006   
ParIS-A Parameterizable Interconnect Switch for Networks-on-Chip  C. A. Zeferino, F. G. M. Espirito Santo, A. A. Susin  17th Symposium on Integrated Circuits and Systems (SBCCI'04)  ACM Press  September 2004  pp.204-209 
PMCNOC: A pipelining multi-channel central caching network-on-chip communication architecture design  N. Wang, A. Sanusi, P. Zhao, S. Mohamed, M. A. Bayoumi    SiPS  Oct. 2007  487-492 
Prediction-based Flow Control for Network-on-Chip Traffic,  U.Y Ogras, R. Marculescu  DAC, 2006    2006  pp. 839-844. 
RASoC: A Router Soft-Core for Networks-on-Chip  C.A. Zeferino, M.E. Kreutz, A.A. Ssin  DATE, 2004  Proceedings, DATE 2004; Volume 3  February 16-20, 2004  198-203 
Reliable network-on-chip based on generalized de Bruijn graph  M. Hosseinabady, M. Kakoee, J. Mathew, D. Pradhan    HLVDT  Nov. 2007  3-10 
Ring road noc architecture  H. Samuelsson, S. Kumar    Norchip  2004  16-19 
SILENT : Serialized Low Energy Transmission Coding for On-Chip Interconnection Networks  Kangmin Lee, Se-Joong Lee, Hoi-Jun Yoo  IEEE ICCAD 2004  Digest of Technical Papers, ICCAD 2004  Nov. 7-11, 2004  Pages: 448-451 
SoCIN: a Parametric and Scalable Network-on-Chip  C. A. Zeferino, A. A. Susin  16th Symposium on Integrated Circuits and Systems, 2003  Proceedings 16th Symposium on Integrated Circuits Systems 03  September 2003  169 - 174 
SPIN: a scalable, packet switched, on-chip micro-network  A. Adriahantenaina  DATE    Mar. 2003  70-73 
Switch-based interconnect architecture for future systems on chip  P. Pande    SPIE, VLSI Circuits and Systems; Volume 5117  May 2003  228-237 
The design and implementation of a low-latency on-chip network  R. Mullins, A. West, S. Moore  ASP-DAC    Jan. 2006   
Trade offs in the design of a router with both guaranteed and best-effort services for network-on-ch  E. Rijpkema, et al.    IEEE Proc. Computers and Digital Techniques; Volume 150, Issue 5  Sep. 2003  294-302 
uspider: a CAD tool for efficient NoC design  S. Evain, J.P. Diguet, D. Houzet    Norchip  Nov. 2004  218-221 

Wiring Problem

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Admitting and Ejecting Flits in Wormhole-switched Networks on Chip  Zhonghai Lu and Axel Jantsch      September 2007  IET Computers & Digital Techniques 1(5):546-556 
Analysis of Worst-Case Delay Bounds for On-Chip Packet-Switching Networks  Yue Qian, Zhonghai Lu and Wenhua Dou      May 2010  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 29(5), pages 802 - 815 
Buffer Optimization in Network-on-Chip Through Flow Regulation  Fahimeh Jafari, Zhonghai Lu, Axel Jantsch, and Mohammad Hossein Yaghmaee      December 2010  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD). 29(12), pages 1973 - 1986 
Cross Clock-Domain TDM Virtual Circuits for Networks on Chips  Zhonghai Lu  ACM/IEEE International Symposium on Networks-on-Chip (NoCS'2011)    May 2011   
Getting to the Bottom of Deep Submicron  D. Sylvester, K. Keutzer  IEEE/ACM ICCAD, 1998  Digest of Technical Papers, ICCAD 1998  November 8-12, 1998  203 - 211 
Impact of small process geometries on microarchitectures in systems on a chip  D. Sylvester, K. Keutzer  Proceedings of the IEEE  Volume 89, Issue 4  April 2001  pp. 467 - 489 
Reducing interconnect cost in NoC through serialized asynchronous links in NOCS   S. Ogg, E. Valli,C.D Alessandro, A. Yakovlev, B. Al-Hashimi, and L.Benini      May 2007  pp.219-219 
System design of full HD MVC decoding on mesh-based multicore NoCs. Microprocessors and Microsystems - Embedded Hardware Design  Ning Ma, Zhonghai Lu, Li-Rong Zheng      March 2011  Embedded Hardware Design 35(2): 217-229 
TDM Virtual-Circuit Configuration for Network-on-Chip  Zhonghai Lu and Axel Jantsch      August, 2008  IEEE Transactions on Very Large Scale Integration Systems (TVLSI), 16(8):1021-1034 
The future of wires  R. Ho, K.W. Mai, M.A. Horowitz  Proceedings of the IEEE  Volume 89, Issue 4  April 2001  pp. 490 - 504 
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