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Bus-based Architectures | Circuit-Switched NoCs | Crossbars | NoC Concept | Optimization, Synthesis and Design Space Exploration | Packet-Switched NoCs | Sockets, Interfaces and Reuse | Wiring Problem

NoC Comparison

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A Comparison of Network-on-Chip and Bussses  Arteris    Design and Reuse  May 30 2005  http://www.us.design-reuse.com/articles/article10496.html 
Reconfigurable fabric interconnects  S. Vassiliadis, I. Sourdis    Int'l Symposium on Soc  Nov. 2006  41-44 
Requirements for Network-on-Chip Benchmarking  Erno Salminen, Tero Kangas, Timo D. Hmlinen, Jouni Riihimki    Norchip, Oulu, Finland, November 21-22, 2005  2005  pp. 82-85 
Distributed Bus Arbitration Algorithm Comparison on FPGA Based MPEG-4 Multiprocessor SoC  A. Kulmala, E. Salminen, T. Hamalainen    IET Computers and Digital Techniques  2008   
Network-on-chip benchmarks specification Part 1: application modeling and hardware description  E. Salminen, C. Grecu, T. Hamalainen, A. Ivanov    OCP-IP  April 2008  15 pages 
Power analysis of link level and end-to-end data protection in networks on chip  A. Jantsch, R. Lauter, A. Vitkowski    ISCAS; Volume 2  2005  1770-1773 
Models for communication tradeoffs on systems-on-chip  C.A. Zeferino, et al.    IP based design  Oct. 2002  394-400 
Packetization and routing analysis of on-chip multiprocessor networks  T.T. Ye, L. Benini, G. de Micheli    Journal of Systems Architecture; Volume 50, Issues 2-3  February 2004  Pages 81-104 
QNoC: QoS architecture and design process for network on chip  E. Bolotin, I. Cidon, R. Ginosar, A. Kolodny, Edited by: A. Jantsch, J. Oberg and H. Tenhunen    Journal of Systems Architecture, Volume 50, Issues 2-3, Special issue on networks on chip  February 2004  105-128, Pages 61-168 
Polaris: a system-level roadmapping toolchain for on-chip interconnection networks  V. Soteriou, et al.    IEEE Trans. VLSI Syst. Vol 15, Issue 8  Aug. 2007  401-408 
Performance evaluation for three-dimensional networks-on-chip  B. Feero, P. Pande    ISVLSI  2007  305-310 
PIRATE: A Framework for Power/Performance Exploration of Network-on-Chip Architectures  G. Palermo, C. Silvano    Lecture Notes in Computer Science, Volume 3254  Jan 2004  521 - 531 
A delay model for router micro-architectures  L.S. Peh, W.J. Dally    IEEE Micro  Jan/Feb 2001  26-34 
Analysis of error recovery schemes for networks on chip  S. Murali, et al.    IEEE Design and Test; Volume 25, Issue 5  2005  434-442 
Flexible bus and NoC performance analysis with configurable synthetic workloads  R. Thid, I. Sander, A. Jantsch    DSD  2006  681-688 
Energy and latency evaluation of NoC topologies  M. Kreutz, et al.    ISCAS; Vol 6  May 2005  5866-5869 
Cost considerations in network on chip  E. Bolotin, I. Cidon, R. Ginosar, A. Kolodny    the VLSI Journal, Vol. 38, Iss. 1  Oct. 2004  19-42 
A statistical traffic model for on-chip interconnection networks  V. Soteriou, H. Wang, L.-S. Peh    MASCOTS  2006  104-116 
Methodology for design, modeling, and analysis of networks-on-chip  J. Xu, et al.    ISCAS  May 2005  1778-1781 
Evaluating SoC Network Performance in MPEG-4 Encoder  A. Kulmala, E. Salminen, M. Hannikainen, T. Hamalainen    The Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology  May 2008  19 pages 
Communication architectures for system-on-chip  M. Kreutz, et al.    SBCCI  2001  14-19 
Evaluation and design trade-offs between circuit-switched and packet-switched NOCs for application  Kuei-Chung Chang, Jih-Sheng Shen, Tien-Fu Chen      July 24 - 28, 2006  143 - 148. 
Evaluation of on-chip networks using deflection routing  Z. Lu, M. Zhong, A. Jantsch    GLSVLSI  May 2006  296-301 
System-level point-to-point communication synthesis using floorplanning information  J. Hu, Y. Deng, R. Marculescu    ASP-DAC/VLSI  Jan. 2002  573-579 
Comparison of synthesized bus and crossbar interconnection architectures  V. Lahtinen, et al.    ISCAS; Vol 5  May 2003  433-436 
Topology adaptive network-on-chip design and implementation  T. Bartic    IEE Proc. Comput. Digit. Tech; Vol 152, Issue 4  Jul. 2005  467-472 
Benchmarking mesh and hierarchical bus networks in system-on-chip context  E. Salminen    Journal of Systems Architectures; Volume 53, Issue 8  Aug. 2007  477-488 
Network-on-chip benchmarking specification Part 2: Microbenchmark Specification version 1.0  Z. Lu, A. Jantsch, E. Salminen, C. Grecu    OCP-IP  June 2008  16 pages 
A layout-aware analysis of networks-on-chip and traditional interconnects for MPSoCs  F. Angiolini, P. Meloni, S. Carta, L. Raffo, and L. Benini      Mar. 2007  IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 3,pp. 421-434 
An Energy and Performance Exploration of Network-on-Chip Architectures  A. Banerjee, P.T. Wolkotte, R.D. Mullins, S.W. Moore, G.J.M. Smit      March 2009   IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 17, no. 3, pp. 319-329 
T.Bartic, J.-Y.Mignolet,V.Nollet,T.Marescaux,D.Verkest,S.Vernalde, and R. Lauwereins  Topology adaptive network-on-chip design and implementation      Jul. 2005  IEEE Proc. Comput. Digit. Tech., vol. 152, no. 4, pp. 467-472 
Error control schemes for on-chip communication links: the energy-reliability tradeoff  D. Bertozzi, L.Benini,and G. de Micheli      Jun. 2005  IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol.24, no. 6, pp.818-831 
Networks-on-Chip in a Three-Dimensional Environment: A Performance Evaluation. IEEE Trans. Computers 58(1)  B. Feero, P.P. Pande      2009  pp. 32-45 
Quality-of-service and error control techniques for mesh-based network-on-chip architectures  P.Vellanki, N.Banerjee,and K.S.Chatha      Jan.2005  Integration, the VLSI Journal,vol.38,no.3,pp.353-382 
A delay model for router micro-architectures  L.-S.Peh and W.J. Dally      Jan/Feb.2001  IEEE Micro, pp.26-34 
Polaris:Asystem-level roadmapping toolchain for on-chip interconnection networks  V.Soteriou, N. Eisley, H. Wang, B.Li, and L.-S. Peh      Aug.2007  IEEETrans. VLSI Syst., vol.15, no.8, pp.855-868 
The Power Analysis of Interconnect Structures  Yan Zhang, Wu Ye, R.M. Owens, M.J. Irwin  10th Annual IEEE International ASIC Conference, 1997  Proceedings, 10th Annual IEEE International ASIC Conf., 1997  1997  25-29 
High Level Estimation of the Area and Power Consumption of On-Chip Interconnects  D. Langen, A. Brinkmann, U. Rckert  13th Annual IEEE International ASIC/SOC Conference  Proceedings, 13th Annual IEEE International ASIC/SOC Conf  2000  297-301 
Performance Analysis of Systems with Multi-Channel Communication Architectures  K. Lahiri, A. Raghunathan, S. Dey  13th International Conference on VLSI Design  Proceedings, 13th International Conference on VLSI Design  January 2000  530-537 
Communication architectures for system-on-chip  M.E. Kreutz, L. Carro, C.A. Zeferino, A.A. Susin  14th Symposium on Ingegrated Circuits and Systems Design    2001  14 - 19 
A Study on Communication Issues for Systems-on-Chip  C. A. Zeferino, M. E. Kreutz, L. Carro, A. A. Susin  15th Symposium on Integrated Circuits & Systems (SBCCI),2002  Proceedings, 15th SBCCI 2002  2002  121-126 
Fault tolerance overhead in network-on-chip flow control  Pullini, F. Angiolini, D. Bertozzi, L. Benini  18th annual symposium on Integrated circuits and system design (SBCCI), Florianolpolis, France, 2005    2005  224 - 229 
Power analysis of system-level on-chip communication architectures  Kanishka Lahiri, Anand Raghunathan  Conference on Hardware/Software Codesign and System Synthesis (CODES + ISSS), Stockholm, Sweden    Sept. 8-10, 2004  pp. 236 - 241 
Evaluation of the traffic-performance characteristics of system-on-chip communication architectures  K. Lahiri, A. Raghunathan, S. Dey  Conference on VLSI Design    2001  29-35 
Design space exploration and prototyping for on-chip multimedia applications  H. G. Lee, et al.  DAC    Jul. 2006  137-142 
A Network Traffic Generator Model for  S. Mahadevan, M. Storgaard, R. Olsen, J. Sparsoe, J. Madsen, F. Angiolini, and L. Benini  DATE 2005    2005  pp. 780-785 
Analyzing on-chip communication in a MPSoC environment  M. Loghi, F.Angiolini, D. Bertozzi, L. Benini, and R. Zafalon  DATE Feb.2004      pp. 752-757 
Automated Bus Generation for Multiprocessor SoC Design  K. Ryu, V. Mooney  Design Automation and Test in Europe (DATE) 2003  Proceedings, DATE 2003  March 2003  282-287 
Analysis of Power Consumption on Switch Fabrics in Networks Routers  T.T. Ye, L. Benini, G. de Michelli  Design Automation Conference (DAC) 2002  Proceedings, DAC 2002  2002  524-529 
Contrasting a NoC and a Traditional Interconnect Fabric with Layout Awareness  F. Angiolini, P. Meloni, S. Carta, L. Benini, L. Raffo  Design, Automation and Test in Europe (DATE)    06-10 March 2006  Vol. 1, pp. 1- 6 
Flexible MPSoC Platform with Fast Interconnect Exploration for Optimal System Performance  F. Dumitrascu, I. Bacivarov, L. Pieralisi, M. Bonaciu, A.A. Jerraya  Design, Automation and Test in Europe (DATE)  Vol. 2, 06-10  March 2006  1-6 
SPIN: a Scalable, Packet Switched, on-chip Micro-network  A. Adriahantenaina, H. Charlery, A. Greiner, L. Mortiez, C.A. Zeferino  Design, Automation and Test in Europe (DATE) 2003  Proceedings, DATE 2003  2003  70-73 
Analyzing on-chip Communication in a MPSoC Environment  M. Loghi, F. Angiolini, D Bertozzi, L. Benini, R. Zafalon  Design, Automation and Test in Europe (DATE) 2004  Proceedings, DATE 2004 Volume: 2  February 16-20, 2004  752-757 
On Network-on-Chip Comparison  E. Salminen, A. Kulmala, T. Hamalainen  Euromicro Conference on Digital System Design    August 27-31, 2007  503-510 
Traffic configuration for evaluating networks on chips  Zhonghai Lu, A. Jantsch  Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC)    20-24 July 2005  pp. 535 - 540 
A Generic Traffic Model for On-Chip Interconnection Networks  Jun Ho Bahn and N. Bagherzadeh - Qualcomm Inc., USA and UC Irvine, USA  First International Workshop on Network on Chip Architectures    November 8th, 2008  8 
Power Comparison of Throughput Optimized IC Busses  E. Malley, A. Salinas, K. Ismail, L. Pileggi  IEEE Computer Society Annual Symposium on VLSI, 2003  Proceedings. IEEE Computer Society Annual Symposium on VLSI  February 20-21, 2003  35-44 
Interconnect Architecture Exploration for Low-Energy Reconfigurable Single-Chip DSPs  Hui Zhang, M. Wan, G. Varghese, J. Rabaey  IEEE Computer Society Annual Workshop on VLSI    April 8-9, 1999  pp. 2-8 
Comparison of Synthesized Bus and Crossbar Interconnection Architectures  V. Lahtinen, E. Salminen, K. Kuusilinna, T. Hmlinen  IEEE International Symposium on Circuits and Systems 2003 (ISCAS 2003)    May 25 - 28, 2003  V-433 -V-436 
Evaluating NoC Communication Backbones with Simulation  R. Thid, M. Millberg, A. Jantsch  IEEE NorChip Conference  Proceedings, IEEE NorChip Conference  November 2003  27-30 
Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures  P.P. Pande, C. Grecu, M. Jones, A. Ivanov, R. Saleh  IEEE Transactions on Computers  Volume 54, Issue 8  Aug. 2005  pp. 1025 - 1040 
Evaluating application mapping using network simulation  T. Salminen, J.-P. Soininen  In International Symposium on System-on-Chip    November 19-21 2003  pp.27-30 
A case study in networks-on-chip design for embedded video  J. Xu, W. Wolf, J. Henkel, S. Chakradhar, T. Lv  In Proceedings of Design Automation and Test in Europe Conference and Exhibition (DATE)    6-20 Feb. 2004  Vol. 2, pp. 770 - 775 
The impact of communication on the scalability of the data-parallel video encoder on MPSoC  E. Salminen, T. Kangas, T. Hamalainen  Int'l Symposium on Soc    Nov. 2006  191-194 
Evaluation of current QoS mechanisms in network-on-chip  A. Mello, L. Tedesco, N. Calazans, F. Moraes  Int'l Symposium on Soc    Nov. 3006  115-118 
Comparative analysis of serial vs parallel links in noc  A. Morgenshtein, I. Cidon, A. Kolodny, R. Ginosar  Int'l Symposium on Soc    2004  185-188 
Interconnections in multi-core architectures: understanding mechanisms, overheads and scaling  R. Kumar, V. Zyuban, D.M.Tullsen  International Symposium on Computer Architecture (ISCA)    4-8 June 2005  408 - 419 
Hierarchical Interconnects for On-chip Clustering  A. Aggarwal, M. Franklin  IPDPS 2002  Proceedings, IPDPS 2002, Abstracts and CD-ROM  2002  602-609 
Trade-offs in the configuration of a network on chip for multiple use-cases  A. Hansson and K. Goossens  NOCS, May 2007    2007  pp.233-242 
The impact of higher communication layers on NoC supported MP-SoCs  T. Marescaux, E. Brockmeyer, and H.Corporaal  NOCS, May 2007      pp. 107-116 
Benchmarking of On-Chip Interconnection Networks  Daniel Wiklund, Sumant Sathe, and Dake Liu  Proc of the International Conference on Microelectronics (ICM), Carthage, Tunisia    Dec. 6-8, 2004  pp. 621 - 624 
Using VCI in a on-chip system  Charlery Herv, Greiner Alain, Encrenaz Emmanuelle, Mortiez Laurent, Andriahantenaina Adrijean  Proceedings of the 11th International Conference Mixed Design of Integrated Circuits and Systems, Szczecin, Poland    June 2004  pp. 571-576 
Orion: a power-performance simulator for interconnection networks  Hang-Sheng Wang, Xinping Zhu, Li-Shiuan Peh, Sharad Malik  Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture    November 18, 2002  294-305 
Comparison of an Aethereal network on chip and traditional interconnects - two case studies  A. Moonen, C. Bartels, M. Bekooij, R. van den Berg, H. Bhullar, K. Goossens, P. Groeneveld, J. Huiskens, J. van Meerbergen,G. De Micheli, S. Mir, R. Reis  Research Trends in VLSI and Systems on Chip, number 249 in IFIP  International Federation for Information Processing  2007  20 

Bus-based Architectures

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A 16Gb/s adaptive bandwidth on-chip bus based on hybrid current/voltage mode signaling  R. Bashirullah, Wentai Liu, R. Cavin, D. Edwards    Digest of Technical Papers Symposium on VLSI Circuits  17-19 June 2004  pp. 392 - 393 
Bus Architecture of a System on a Chip with User-Configurable System Logic  S. Winegarden    IEEE Journal of Solid-State Circuits, Volume: 35, Issue: 3  March 2000  425- 433 
Interconnection Scheme for Continuous-media Systems-on-a-chip  V. Lahtinen, K. Kuusilinna, T. Kangas, T. Hmlinen    Microprocessors and Microsystems, Volume: 26, Issue 3  April 2002  123-138 
Wrapper-based Bus Implementation Techniques for Performance Improvement and Cost Reduction  K. Anjo, A. Okamura, M. Motomura    IEEE Journal of Solid-State Circuits;  May 2004  804-817 
Pipelined Bidirectional Bus Architecture for Embedded Multimedia  Gang-Hoon Seo, Won-Yong Jung, Seongsoo Lee, Jae-Kyung Wee,    Lecture Notes in Computer Science, Volume 3824,  Nov 2005  Pages 350 - 359 
A hybrid SoC interconnect with dynamic TDMA-based transaction-less buses and on-chip networks  T. Richardson, et al.    VLSI Design  Jan. 2006   
A Single-Chip, 1.6-Billion, 16-b MAC/s Multiprocessor DSP  B. Ackland, A. Anesko, D. Brinthaupt, S. J. Daubert, A. Kalavade, J. Knobloch, E. Micca, M. Moturi, C. J. Nicol, J. H. O'Neill, J. Othmer, E. Sckinger, K. J. Singh, J. Sweet, C. J. Terman, and J. Williams    IEEE Journal of Solid-State Circuits, Volume: 35, Issue: 3  March 2000  412-424 
HIBI Communication Network for System-on-Chip  E. Salminen, T. Kangas, J. Riihimaki, V. Lahtinen, K. Kuusilinna, T. Hamalainen    Journal of VLSI Signal Processing-Systems for Signal, Image and Video Technology; Volume 43, Issue 2-3  June 2006  185-205 
MARBLE: an Asynchronous on-chip Macrocell Bus  W.J. Bainbridge, S.B. Furber    Microprocessors and Microsystems 24  2000  213-222 
A2B Synchronous System Bus and A2R Register/Peripheral Bus in an ARC Based Multiprocessor System-on-  Advanced Architectures    Application Note: AN003  2001   
HIBI v.2 Interconnection Network for System-on-Chip  E. Salminen, V. Lahtinen, T. Kangas, J. Riihimki, K. Kuusilinna, T.D. Hmlinen    LNCS 3133 Computer Systems: Architectures, Modeling and Simulation (SAMOS)  2004  412-422 
AHB-Lite overview  ARM Ltd.    ARM SDVI 0044A  2001   
White paper: CoreConnect Bus Architecture  IBM Corporation      1999   
A 600-MHz Single-Chip Multiprocessor with 4.8-GB/s Internal Shared Pipelined Bus and 512-kB Internal  S. Kaneko, H. Kondo, N. Masui, K. Ishimi, T. Itou, M. Satou, N. Okumura, Y. Takata, H. Takata, M. Sakugawa, T. Higuchi, S. Ohtani, K. Sakamoto, N. Ishikawa, M. Nakajima, S. Iwata, K. Hayase, S. Nakano, S. Nakazawa, K. Yamada, T. Shimizu    IEEE Journal of Solid-State Circuits;  January 2004  184-193 
Open Microprocessors Systems Initiative, PI-Bus VHDL Toolkit Version 3.1  M. Bassett, P. Lister, University of Sussex    Open Micro-processor Systems Initiative (OMI) Concertation M  November 8-9, 1994   
Multi-layer AHB Overview  ARM Ltd.    ARM DVI 0045A  2001   
Bus Structures as the Basic Building Blocks of Network-on-Chip  V. Lahtinen, E. Salminen, K. Kuusilinna, T. Hmlinen; Eds. J. Nurmi, H. Tenhunen, J. Isoaho, A. Jantsch    Interconnect-Centric Design for Advanced SoC and NoC; Kluwer  2004  207-230 
Buses  W.W. Hsu, Jih-Kwon Peir, A.B. Tucker, Jr. (Editor-in-Chief)    The Computer Science and Engineering Handbook, CRC Press in  1997  40 pages 
Viper: A Multiprocessor SOC for Advanced Set-top Box and Digital TV Systems  S. Dutta, R. Jensen, A. Rieckmann    IEEE Design & Test of Computers, Volume: 18, Issue: 5  September-October 2001  21-31 
A high performance bus communication architecture through bus splitting  Ruibing Lu, Cheng-Kok Koh    Proceedings of the Asia and South Pacific Design Automation  27-30 Jan. 2004  pp. 751 - 755 
Prefetching for Improved Bus Wrapper Performance in Cores  R. Lysecky, F. Vahid    ACM Transactions on Design Automation of Electronic Systems  January 2002   
Specification for the: WISHBONE System-on-Chip (SoC) Interconnection Architecture for Portable IP Co      Revision: B.3  September 7, 2002   
Next Generation CoreConnect/spl Trade/ Processor Local Bus Architecture  Hofmann, R., Drerup, B  15th Annual IEEE International ASIC/SOC Conference, 2002    September 25-28, 2002  221- 225 
Standard Bus vs. Bus Wrapper: Comparisons and Proposition of a Mixed Approach  M. Bertola, G. Bois, G. Cyr  2002 International Workshop on System-on-Chip for Real-Time    July 2002   
AMBA AXI Protocol Revision:r0p0 Specification  ARM Ltd.  2003 Altera  Avalon Bus Sepcification Reference Manual 2.3  July 2003  106 pages 
An Alternative Architecture for on-chip Global Interconnect: Segmented Bus Power Modeling  Yan Zhang, Wu Ye, M.J. Irwin  32nd Asilomar Conference on Signals, Systems & Computers, 19  Conference Record, 32nd Asilomar Conference on Signals Syste  1998  1062-1065 
Asynchronous Macrocell Interconnect Using MARBLE  W.J. Bainbridge, S.B. Furber  4th International Symposium on Advanced Research in Asynchronous Circuits and Systems  Proceedings, 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems  March 30-April 2, 1998  122-132 
A dual round-robin arbiter for split-transaction buses in system-on-chip implementations  J. Reed, N. Manjikian  Canadian Conference on Electrical and Computer Engineering; Volume 2    May 2004  pp. 835 - 840 
ARM7100-a High-Integration, Low-power Microcontroller for PDA applications  G. Budd, G. Milne  Compcon 1996  Technologies for the Information Superhighway Digest  1996  182-187 
Efficient exploration of on-chip bus architectures and memory allocation  Sungchan Kim, Chaeseok Im, Soonhoi Ha  Conference on Hardware/Software Codesign and System Synthesis (CODES + ISSS), Stockholm, Sweden    8-10 Sept. 2004  pp. 248 - 253 
The Design and Test of a Smartcard Chip Using a CHAIN Self-timed Network-on-Chip  W.J. Bainbridge, L.A. Plana, S.B. Furber  Design Automation and Test in Europe (DATE) 2004  Proceedings, DATE 2004; Volume 3  February 16-20, 2004  274-279 
System Level Power Modeling and Simulation of High-end Industrial Network-on-Chip  A. Bona, V. Zaccaria, R. Zafalon  Design Automation and Test in Europe (DATE) 2004  Proceedings, DATE 2004;  February 16-20, 2004  318-323 
Performance analysis of different arbitration algorithms of the AMBA AHB bus  M. Conti, M. Caldari, G.B. Vece, S. Orcioni, C. Turchetti  Design Automation Conference (DAC)    June 7-11, 2004  pp. 618 - 621 
FLEXBUS: A High Performance System-on-Chip Communication Architecture with a Dynamically Configurabl  K. Sekar, K. Lahiri, A. Raghunathan, S. Dey  Design Automation Conference (DAC)  Proc. Design Automation Conference  June 2005  571 - 574 
LOTTERYBUS: A New HighPerformance Communication Architecture for System-on-Chip Designs  K. Lahiri, A. Raghunathan, G. Lakshminarayana  Design Automation Conference (DAC) 2001  Proceedings, DAC 2001  2001  15-20 
MicroNetwork-based Integration for SoCs  D. Wingard  Design Automation Conference (DAC) 2001  Proceedings, DAC 2001  2001  673-677 
Multi-core SoC Platfrom Integration Using AMBA  R.L. Veal, L. Petrosian, N. Stollon  DesignCon 2002    2002   
Low-Latency Interconnection For IP-Block Based Multimedia Chips  K. Kuusilinna, T. Hamalainen, P. Liimatainen, J. Saarinen  IASTED International Conference Parallel and Distributed Com    December 14-16, 1998  411-416 
An Efficient Bus Architecture for System-on-chip Design  B. Cordan  IEEE CICC 1999  Proceedings, IEEE CICC 1999  May 16-19, 1999  623- 626 
NECoBus: a High-end SOC Bus with a Portable and Low-latency Wrapper-based Interface Mechanism  K. Anjo, A. Okamura, T. Kajiwara, N. Mizushima, M. Omori, Y. Kuroda  IEEE CICC 2002  Proceedings, IEEE CICC 2002  May 12-15, 2002  315- 318 
Integration Architecture for System-on-a-chip Design  D. Wingard, A. Kurosawa  IEEE Custom Integrated Circuits Conference (CICC) 1998  Proceedings, IEEE CICC1998  May 11-14, 1998  85-88 
Self-timed ring architecture for SOC applications  P. Liljeberg, J. Plosila, J. Isoaho  IEEE International SOC [Systems-on-Chip] Conference    September 2003  pp. 359- 362 
AMBA: Enabling Reusable On-Chip Designs  D. Flynn  IEEE Micro  Volume: 17, Issue 4  July-August 1997  20-27 
SNP: a new communication protocol for SoC  Jaesung Lee, Hyuk-Jae Lee, Chanho Lee  International Conference on Communications, Circuits and Sys    27-29 June 2004  Vol. 2, pp. 1419 - 1423 
Design of AMBA wrappers for multiple-clock operations  Nam-Joon Kim, Hyuk-Jae Lee  International Conference on Communications, Circuits and Systems (ICCCAS)    27-29 June 2004  Vol.2, pp. 1438 - 1442 
Samba-bus: a High Performance Bus Architecture for System-on-chips  Ruibing Lu; Cheng-Kok Koh  International Conference on Computer Aided Design (ICCAD)    November 9-13, 2003  8-12 
Efficient Modeling and Synthesis of On-Chip Communication Protocols for Network-on-Chip Design  Robert Siegmund and Dietmar Muller  International Symposium on Circuits and Systems (ISCAS) 2003    2003   
Reconfigurable Memory Bus Systems using Multi-Gbps/pin CDMA I/O Transceivers  Jongsun Kim, Zhiwei Xu, Frank Chang  ISCAS 2003  Proceedings, ISCAS 2003 Volume: 2  2003  II-33- II-36 
Fast Exploration of Bus-based On-chip Communication  S. Pasricha, N. Dutt, M. Ben-Romdhane  Proceedings of international conference on Hardware/software codesign and system synthesis (CODES)    8-10 September 2004  pp 242 - 247 
Arbitration for the segmented bus architecture  T. Seceleanu, S. Stancescu  Proceedings of Internatioanl Semiconductor Conference (CAS)    4-6 Oct. 2004  pp. 487 - 490 

Circuit-Switched NoCs

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Design of a switching node (router) for on-chip networks  S. Sathe, D. Wiklund, D. Liu    ASIC  Oct. 2003  75-78 
On a design of crossroad switches for low-power on-chip communication architectures  J.-S. Chen, K.-C. Chang, T.-F. Chen    ISCAS  May 2006   
Switched interconnect for system-on-chip designs  D. Wiklund, D. Liu    IP2000  Oct. 2000  192-198 
An energy-efficient reconfigurable circuit-switched network-on-chip  P. Wolkotte, et al.    IPDPS  Apr. 2005  155a 
An architecture and compiler for scalable on-chip communication  J. Liang    IEEE Trans. VLSI Syst.; Vol. 12, Issue 7  2004  711-726 
Spatial division multiplexing: a novel approach for guaranteed  A. Leroy, P. Marchal, A. Shickova, F. Catthoor, F. Robert, D. Verkest  CODES+ISSS05, Jersey City, New Jersey, USA    Sept. 1921, 2005  pp .81-86 
Cost-Performance Trade-offs in Networks-on-Chip: A Simulation-Based Approach  S.G. Pestana, E. Rijpkema, A. Radulescu, K. Goossens, O.P. Gangwal  DATE, 2004  Proceedings, DATE 2004; Volume 2  February 16-20, 2004  764-769 
A Case Study in Networks-on-Chip Design for Embedded Video  J. Xu, W. Wolf, J. Henkel, S. Chakradhar  DATE, 2004  Proceedings, DATE 2004; Volume 2  February 16-20, 2004  770-775 
A flexible circuit switched NOC for FPGA based sytems  C. Hilton, B. Nelson  FPL    2005  24-26 
An Energy-Efficient Reconfigurable Circuit-Switched Network-on-Chip  P.T. Wolkotte, G.J.M. Smit, G.K. Rauwerda, L.T. Smit  Proceedings of IEEE International Parallel and Distributed Processing Symposium (IPDPS)    04-08 April 2005  pp. 155a - 155a 

Crossbars

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Piranha: a Scalable Architecture Based on Single-chip Multiprocessing  L.A. Barroso, K. Gharachorloo, R. McNamara, A. Nowatzyk, S. Qadeer, B. Sano, S. Smith, R. Stets, B. Verghese    ACM SIGARCH Computer Architecture News, Volume: 28, Issue 2  May 2000  282- 293 
A Two-Level On-Chip Bus System Based on Multiplexers  Kyoung-Sun Jhang, Kang Yi, Soo Yun Hwang    Lecture Notes in Computer Science, Vol. 3189  Jan 2004  363 - 372 
A new multi-channel on-chip bus architecture for system-on-chips  S. Lee, C. Lee, H.-J. Lee    SOCC  Sep. 2004  305-308 
Where Buses Cannot Go  A. Boxer    IEEE Spectrum, Volume: 32, Issue: 2  February 1995  41-45 
METRO: a Router Architecture for High-Performance, Short-haul Routing Networks  A. DeHon, F. Chong, M. Becker, E. Egozy, H. Minsky, S. Peretz, T.F. Knight Jr.  21st Annual International Symposium on Computer Architecture  Proceedings, 21st Annual International Symposium on Computer  April 18-21, 1994  266-277 
A Flexible Virtual Platform for Computational and Communication Architecture Exploration of DMT VDSL  S. Brini, D. Benjelloun, F. Castanier  Design Automation and Test in Europe (DATE), 2003    2003  164-169 
A Multiprocessor DSP System Using PADDI-2  R.A. Sutton, V.P. Srini, J.M. Rabaey  Design Automation Conference(DAC), 1998    1998  62 
Stream Communication Between Real-Time Tasks in a High-Performance Multiprocessor  J.A.J. Leijten, J.L. van Meerbergen, A.H. Timmer, J.A.G Jess  Design, Automation and Test in Europe (DATE), 1998  Proceedings, DATE 1998  February 23-26, 1998  125- 131 
A new multi-channel on-chip-bus architecture for system-on-chips  Sanghun Lee Chanho Lee Hyuk-Jae Lee  IEEE International SOC Conference    12-15 Sept. 2004  305- 308 

NoC Concept

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Towards open network-on-chip benchmarks  C. Grecu, P. Pande, A. Ivanov, R. Marculescu, E. Salminen, A. Jantsch    NOCS  May 2007  205 
A generic architecture for on-chip packet-switched interconnections  P. Guerrier, A. Greiner    DATE  Mar. 2000  250-256 
Networks on silicon: blessing or nightmare?  P. Wielage, K. Goossens    DSD  Sep. 2002  196-200 
Survey of Network-on-chip Proposals  E. Salminen, A. Kulmala, T. Hamalainen    www.ocpip.org/socket/whitepapers  April 9, 2008  13 pages 
3-d topologies for networks-on-chips  V. F. Pavlidis, E. G. Friedman    IEEE Trans. VLSI Syst.  2007   
Interconnect-centric design for advanced SoC and NoC  J. Nurmi, H. Tenhunen, J. Isoaho, A. Jantsch    Doredrecht, The Netherlands: Kluwer Academic Publishers  2004   
Testing network-on-chip communication fabrics  C. Grecu, A. Ivanov, R. Saleh, P. Pande    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems; Volume 26, No. 10  Dec. 2007  2201-2014 
Research challenges for on-chip interconnection networks  J. Owens, et al.    IEEE Micro; Volume 27, Issue 5  Sep-Oct. 2007  96-108 
Network on chip: An architecture for billion transistor era  A. Hermani, A. Jantsch, S. Kumar, A. Postula, J. Oberg, M. Millberg, D. Lindqvist    Norchip  2000   
Networks on Chip  A. Jantsch and H. Tenhunen    Kluwer Academic Publishers  February 2003   
Interconnect-Centric Design for Advanced SoC and NoC  Eds. J. Nurmi, H. Tenhunen, J. Isoaho, A. Jantsch    Kluwer Academic Publishers  2004   
Networks on chips: a new SoC paradigm  Benini, L.; De Micheli, G    Volume: 35 Issue: 1  January 2002  pp. 70 -78 
A survey of research and practices of Network-on-chip  Tobias Bjerregaard, Shankar Mahadevan    ACM Computing Surveys; Volume 38, Issue 1, Article 1  2006  2006 
Networks on chips: technology and tools  L. Benini, G. de Micheli    Morgan Kaufmann  2006   
Extending platform-based design to network on chip systems  J.-P. Soininen, A. Jantsch, M. Forsell, A. Pelkonen, J. Kreku, S. Kumar    VLSI Design  Jan. 2003  401-408 
Essential fault-tolerance metrics for NoC infrastructures, in IOLTS  C. Grecu, L. Anghel, P.P. Pande, A. Ivanov, and R. Saleh    Jul.2007    pp.37-42 
Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives, R. in IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (TCAD)  R. Marculescu, U. Y. Ogras, L.-S. Peh, N. E. Jerger, Y. Hoskote    Jan. 2009.    vol. 28, no. 1, pp. 3-21 
On-Chip Networks: A Scalable, Communication-Centric Embedded System Design Paradigm  J. Henkel, W. Wolf, S. Chakradhar  17th International Conference on VLSI Design  Proceedings, 17th International Conference on VLSI Design  January 5-9  845-851 
System-Level Point-to-Point Communication Synthesis Using Floorplanning Information  Jingcao Hu, Yangdong Deng, R. Marculescu  ASP-DAC/VLSI    January 2002  pp. 573 - 579 
Towards on-chip fault-tolerant communication  T. Dumitras, S. Kerner, R. Marculescu  ASP/DAC, 2003  Proceedings, ASP/DAC 2003  January 21-24, 2003  225 - 232 
Key research problems in NoC design: a holistic perspective  Umit Y. Ogras, Jingcao Hu, Radu Marculescu  CODES 2005    2005  pp. 69-75 
Route Packets, Not Wires: on-chip Interconnection Networks  W.J. Dally, B. Towles  Design Automation Conference (DAC), 2001  Proceedings, DAC 2001  2001  684 
Networks on Chips: From research to products  G. De Micheli, C. Seiculescu, S. Murali, L. Benini, F. Angiolini, A. Pullini  Design Automation Conference (DAC), 2010    2010  pp. 300 - 305 
Coping with latency in SOC design  L.P. Carloni, A.L. Sangiovanni-Vincentelli  IEEE Micro  Volume 22, Issue 5  Sept-Oct. 2002  pp. 24 - 35 
An Autonomous Error-tolerant Cell for Scalable Network-on-Chip Architectures  Valtonen, T., J. Isoaho, H. Tenhunen  In Proceedings Norchip    2001  pp. 198 - 203 
A network on chip architecture and design methodology  S. Kumar, A. Jantsch, J.-P. Soininen, M. Forsell, M. Millberg, J. berg, K. Tiensyrj, and A. Hemani  In Proceedings of IEEE Computer Society Annual Symposium on VLSI    April 2002   

Optimization, Synthesis and Design Space Exploration

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Developing Architectural Patforms: a Disciplined Approach  A. Mihal, C. Kulkarni, M. Moskewicz, M. Tsai, N. Shah, S. Weber, Yujia Jin, K.Keutzer, K. Vissers, C. Sauer, S. Malik    IEEE Design & Test of Computers, Volume: 19, Issue: 6  November-December 2002  6-16 
Power-driven Design of Router Microarchitectures in On-chip Networks  Hangsheng Wang, Li-Shiuan Peh and Sharad Malik    Proceedings of MICRO 36, San Diego  Nov 2003  pp. 105 - 116 
UML-based Multi-Processor SoC Design Framework  T. Kangas    ACM Transactions on Embedded Computing Systems, Vol. 5, No. 2  May 2006  281-320 
Managing Power Consumption in Networks-on-Chips  T. Simunic, S.P. Boyd, P. Glynn,    IEEE Transactions on Very Large Scale Integration (VLSI)Syst  January 2004  96-107 
A Communication-Centric Design Flow for HIBI-based SoC's  T. Kangas, J. Riihimaki, E. Salminen, V. Lahtinen, H. Orsila, K. Kuusilinna, T.D. Hamalainen, S. Vassiliadis    LNCS 3133 Computer Systems: Architectures, Modeling and Simulation (SAMOS)  2004  474-483 
Early ISS Integration Into Network-on-Chip Designs  A. Wieferink, M. Doerper, T. Kogel, R. Leupers, G. Asceid, H. Meyr    LNCS 3133 Computer Systems: Architectures, Modeling and Simulation (SAMOS)  2004  443-451 
Design Space Exploration for Optimizing System-on-Chip Communication Architectures  K. Lahiri, A. Raghunathan, S. Dey    IEEE Transactions on Computer-Aided Design of Integrated Circuits; Volume 23, Issue 6  June 2004  952-961 
UML-based Multi-Processor SoC Design Framework  T. Kangas, P. Kukkala, H. Orsila, E. Salminen, M. Hännikäinen, T. Hämäläinen, J. Riihimäki, K. Kuusilinna    ACM Transactions on Embedded Computing Systems, Vol. 5, No. 2  May 2006  281-320 
Socket-Based Design Using Decoupled Interconnects  D. Wingard    ESSIRC from "Interconnect-Centric Design for SoC and NoC" tu  September 2003   
Performance Analysis of SoC Communication by Application of Deterministic and Stochastic Petri Nets  H. Blume, T. von Sydow, T.G. Noll    LNCS 3133 Computer Systems: Architectures, Modeling and Simulation (SAMOS)  2004  484-493 
Dynamic Voltage Scaling with Links for Power Optimization of Interconnection Networks  Li Shang, Li-Shiuan Peh, and Niraj Jha    Symp. on High Performance Computer Architecture (HPCA)  8-12 Feb. 2003  105 - 116 
Design of High-Performance System-on-Chips Using Communication Architecture Tuners  K. Lahiri, A. Raghunathan, G. Lakshminarayana, S. Dey    IEEE Transactions on Computer-Aided Design of Integrated Circuits; Volume 23, Issue 5  May 2004  620-636 
Combining a Performance Estimation Methodology with a Hardware/software Codesign Flow Supporting Mul  A. Baghdadi, W.O. Cesario, A.A. Jerraya, N.-E. Zergainoh    IEEE Transactions on Software Engineering, Volume: 28, Issue 9  September 2002  822-831 
Synthesis of Predictable Networks-on-Chip-Based Interconnect Architectures for Chip Multiprocessors, IEEE Trans. Very Large Scale Integration (VLSI) Systems, Vol. 15, Iss. 8  S. Murali, D. Atienza, P. Meloni, S. Carta, L. Benini, G De Micheli, L. Raffo      2007  869-880 
A DRAM Centric NoC Architecture and Topology Design Approach , IEEE Computer Society Annual Symposium on VLSI (ISVLSI)  C. Seiculescu, S. Murali, L. Benini, G. De Micheli    2011  2011  pp. 54 - 59 
NoCGEN: A Template Based Reuse Methodology for Networks-on-Chip Architecture  J. Chan, S. Parameswaran  17th International Conference on VLSI Design  Proceedings, Conference on VLSI Design 2004  January 5-9, 2004  717-720 
Bus Architecture Synthesis for Hardware-Software Co-design of Deep Submicron Systems on Chip  N. Thepayasuwan, V. Damle, A. Doboli  21st International Conference on Computer Design  Proceedings, 21st International Conference on C.D.  October 13-15, 2003  126-133 
xpipes: A Latency Insensitive Parameterized Network-on-Chip Architecture for Multi-processor SoCs  M. Dall'Osso, G. Biccari, L. Giovannini, D. Bertozzi, L. Benini  21st International Conference on Computer Design, 2003  Proceedings, 21st International Conference on C.D.  October 13-15, 2003  536-539 
A Practical Tool Box for System Level Communication Synthesis  D. Hommais, F. Petrot, I. Auge  9th CODES 2001  Proceedings, CODES 2001  April 25-27, 2001  48-53 
Communication analysis for system-on-chip design  A. Siebenborn, O. Bringmann, W. Rosenstiel  DATE 2004    16-20 Feb. 2004  Vol.1 pp. 648 - 653 
Synthesis of Communication Interface for SoC Using VSIA Recommendations  G. Cyr, G. Bois, M. Aboulhamid  Design Automation and Test in Europe (DATE) 2001  Proceedings, DATE 2001  2001  155-159 
Exploiting the Routing Flexibility for Energy/perf. Aware of Mapping of Regular NoC Architectures  Jingcao Hu, R. Marculescu  Design Automation and Test in Europe (DATE) 2003  Proceedings, DATE 2003  March 3-7, 2003  688-693 
A Multi-Level Design Flow for Incorporating IP Cores: Case Study of 1D Wavelet IP Integration  A. Baganne, I. Bennour, M. Elmarzougui, R. Gaiech, and E. Martin  Design Automation and Test in Europe (DATE) 2003    March 3-7, 2003  pp. 250-255 
A Power and Performance Model for Network-on-Chip Architectures  N. Banjerjee, P. Vellanki, K.S. Chatha  Design Automation and Test in Europe (DATE) 2004  Proceedings, DATE 2004 Volume: 2  February 16-20, 2004  1250-1255 
An interconnect channel design methodology for high performance integrated circuits  V. Chandra, A. Xu, H. Schmit, L. Pileggi  Design Automation and Test in Europe (DATE) 2004  Proceedings, DATE  February 16-20, 2004  Vol. 2 pp. 1138-1143 
xpipesCompiler: a Tool for Instantiating Application Specific Networks on Chip  A. Jalabert, S. Murali, L. Benini, G. DeMichel  Design Automation and Test in Europe (DATE) 2004  Proceedings, DATE 2004 Volume: 2  February 16-20, 2004  884-889 
Fast exploration of parameterized bus architecture for communication-centric SoC design  C. Shin, Y-T. Kim, E-Y. Chung, K-M. Choi, J.-T. Kong, S. Eo  Design Automation and Test in Europe Conference and Exhibition (DATE)    February 16-20, 2004  Vol. 1, 352 - 357 
Addressing the System-on-a-Chip Interconnect Woes Through Communication-based Design  M. Sgroi, M. Sheets, A. Mihal, K. Kuetzer, S. Malik, J. Rabaey, A. Sangiovanni-Vincentelli  Design Automation Conference (DAC) 2001  Proceedings, DAC 2001  2001  667-672 
High-level Specification and Automatic Generation of IP Interface Monitors  M.T. Oliveira, A.J. Hu  Design Automation Conference (DAC) 2002  Proceedings, DAC 2002  June 10-14, 2002  129-134 
SUNMAP: A Tool for Automatic Topology Selection and Generation for NoCs  S. Murali, G. De Micheli  Design Automation Conference (DAC) 2004    2004  pp. 914 - 919 
OCCN: A Network-on-Chip Modeling and Simulation Framework  M. Coppola, S. Curaba, M.D. Grammatikakis, G. Maruccia, F. Papariello  Design Automation Test in Europe (DATE) 2004  Proceedings, DATE 2004 Volume: 3  February 16-20, 2004  174-179 
Bandwidth-Constrained Mapping of Cores onto NoC Architectures  S. Murali, G. DeMicheli  Design Automation Test in Europe (DATE) 2004  Proceedings, DATE 2004 Volume: 2  February 16-20, 2004  896-901 
A Simulation-based Power-aware Architecture Exploration of a Multiprocessor System-on-Chip Design  F. Menichelli, M. Olivieri, L. Benini, M. Donno, L. Bisdounis  Design Automation Test in Europe (DATE) 2004  Proceedings, DATE 2004 Volume: 3  February 16-20, 2004  312-317 
An Efficient Architecture Model for Systematic Design of Application-specific Microprocessor SoC  A. Baghdadi, A.A. Jerraya, D. Lyonnard, N.E. Zergainoh  Design, Automation and Test in Europe (DATE) 2001  Proceedings, DATE 2001  2001  55-62 
Tiles - An Architectural Abstraction for Platform-Based Design  D. Wingard  EDA Vision    June 2002   
Platform-based Design for Digital Signal Processing Systems: a Case Study of MPEG-2/JPEG2000 Encoder  P. Coussy, A. Baganne, E. Martin  IEEE 2002 International Conference on Circuits and Systems  Volume 2  June 29-July 1, 2002  1361-1366 
A Simulation Based Approach for Incorporating Virtual Components IP Cores into Multimedia Systems De  A. Baganne, I. Bennour, M. Elmarzougui, E. Martin  IEEE ICASSP 2003  Proceedings, ICASSP 2003, Volume: 2  April 6-10, 2003  525-528 
NoC synthesis flow for customized domain specific multiprocessor systems-on-chip  D. Bertozzi, A. Jalabert, Srinivasan Murali, R. Tamhankar, S. Stergiou, L. Benini, G. De Micheli  IEEE Transactions on Parallel and Distributed Systems    Feb 2005  Vol. 16, Iss. 2; pp 113-129 
Linear-Programming-Based Techniques for Synthesis of Network-on-Chip Architectures  Srinivasan, K.; Chatha, K.S.; Konjevod, G.,  IEEE Transactions on VLSI  Volume 14, Issue 4  April 2006  407- 420. 
Communication-Aware Task Scheduling and Voltage Selection for Total Systems Energy Minimization  G. Varatkar, R. Marculescu  International Conference on Computer Aided Design (ICCAD) 20  Proceedings, ICCAD 2003  November 9-13, 2003  pp. 510 - 517 
Interface Design Approach for System on Chip Based on Configuration  I. Maalej, G. Gogniat, M. Abid, J.L. Philippe  International Symposium on Circuits and Systems (ISCAS) 2003  Proceedings, ISCAS Volume: 5  May 25-28, 2003  V-593-596 
Topology Optimization for Application-specific Networks-on-chip  T. Ahonen, D.A. Sigenza-Tortosa, H. Bin, J. Nurmi  International Workshop on System-Level Interconnect Prediction (SLIP)    2004  53-60 
VC Rating and Quality Metrics: Why Bother? [SoC]  P. Bricaud  ISQED 2002  Proceedings, ISQED 2002  March 8-21, 2002  257-260 
Floorplan-aware automated synthesis of bus-based communication architectures  S. Pasricha, N. Dutt, E. Bozorgzadeh, M. Ben-Romdhane  Proc. of Design Automation Conference (DAC)    13-17 June 2005  pp. 565 - 570 
Benchmark-based design strategies for single chip heterogeneous multiprocessors  J.M. Paul, D.E. Thomas, A. Bobrek  Proceedings of international conference on Hardware/software codesign and system synthesis (CODES)    September 8-10, 2004  pp. 54-59 
Optimizing Network Throughput: Optimal Versus Robust Design  P. Lopez, R. Alcover, J. Duato, L. Znica  Seventh Euromicro Workshop on Parallel and Distributed Proce    February 3-5, 1999  45-52 
Towards a communication characterization methodology  S. Chodnekar, V. Srinivasan, A.S. Vaidya, A. Sivasubramaniam, C.R. Das  Third International Symposium on High-Performance Computer Architecture    1-5 Feb. 1997  pp. 310-319 

Packet-Switched NoCs

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MoCSYS: A Multi-Clock Hybrid Two-Layer Router Architecture and Integrated Topology Synthesis Framewo      VLSI Design  2008  397-402 
Low-power network-on-chip for high-performance soc design  K. Lee, S.-J. Lee, H.-J. Yoo    IEEE Trans. VLSI Syst.; Vol 14, Issue 2  Feb. 2006  148-160 
A validation and performance evaluation tool for ProtoNoc  D. Castells-Rufas, J. Joven, J. Carrabina    Int'l Symposium on Soc  Nov. 2006  159-162 
Hermes: an infrastructure for low area overhead packet-switching networks on chip  F. Moraes, et al.    Integration, the VLSI Journal; Vol. 38, Issue 1  Oct. 2004  69-93 
Design and implementation of a routing switch for on-chip interconnection networks  K.-C. Chang, J.-S. Shen, T.-F. Chen    AP-ASIC  Aug. 2004  392-395 
Micro-network for SoC: Implementation of a 32-port SPIN network  A. Andriahantenaina, A. Greiner    DATE  Mar. 2003  1128-1129 
Trade offs in the design of a router with both guaranteed and best-effort services for network-on-ch  E. Rijpkema, et al.    IEEE Proc. Computers and Digital Techniques; Volume 150, Issue 5  Sep. 2003  294-302 
Ring road noc architecture  H. Samuelsson, S. Kumar    Norchip  2004  16-19 
Reliable network-on-chip based on generalized de Bruijn graph  M. Hosseinabady, M. Kakoee, J. Mathew, D. Pradhan    HLVDT  Nov. 2007  3-10 
A high-throughput network-on-chip architecture for systems-on-chip interconnects  A. Bouhraoua, M.E. Elrabaa    Int'l Symposium on Soc  Nov. 2006  127-130 
uspider: a CAD tool for efficient NoC design  S. Evain, J.P. Diguet, D. Houzet    Norchip  Nov. 2004  218-221 
Applying cdma technique to network-on-chip  Xin Wang, T. Ahonen, J. Nurmi    IEEE Trans. VLSI Syst. Volume 15, Issue 10    1091-1100 
PMCNOC: A pipelining multi-channel central caching network-on-chip communication architecture design  N. Wang, A. Sanusi, P. Zhao, S. Mohamed, M. A. Bayoumi    SiPS  Oct. 2007  487-492 
An 80-tile Sub-100-W TeraFLOPS processor in 65-nm CMOS  S. Vangal, et al.    IEEE J. Solid-State Circuits; Volume 43, Issue 1  Jan. 2007  29-41 
An 81.6 GOPS object recognition processor based on noc and visual image processing memory  D. Kim, M. Kim, J.-Y. Kim, S. Lee, H.-J. Yoo      CICC   
A reconfigurable baseband platform based on an asynchronous network-on-chip  D. Lattard, et al.    IEEE J. Solid-State Circuits; Volume 43, Issue 1  223-235   
A Scalable Embedded On-Chip Multiprocessor Architecture for Network Applications  J. Niemann, C. Puttmann, M. Porrmann, U. Rückert    Lecture Notes in Computer Science, Volume 3894  Feb 2006  268 - 282 
Panacea - a case study on the panacea noc - a nostrum network on chip prototype  E. Nilsson, J. Oberg    Royal Institute of Technology, Tech. Rep. 229  Apr. 2006   
Hermes project web page  A.V. de Mello, L.H. Moller    http://toledo.inf.pucrs.br/gaph/Projects/Hermes/Hermes.html  2004   
Hierarchical Graph: A New Cost Effective Architecture for Network on Chip  A. Vahdatpour, A. Tavakoli, M. Falaki    Lecture Notes in Computer Science, Volume 3824,  Nov 2005  Pages 311 - 320 
Communication architecture optimization: making the shortest path shorter in regular networks-on-chi  U. Ogras, et al.    DATE  Mar. 2006   
An interconnect architecture for networking systems on chips  F. Karim, A. Nguyen, S. Dey    IEEE Micro; Vol 22, Issue 5  Sep.-Oct. 2002  36-45 
Issues in the development of a practical NoC: the Proteo concept  D. Siguenza-Tortosa, T. Ahonen, J. Nurmi    Integration, the VLSI Journal, Vol. 38, Issue 1  Oct. 2004  95-105 
An efficient on-chip NI offering guaranteed services, shared-memory abstraction, and flexible networ  A. Radulescu, et al.    IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems; Vol. 21, Issue 1  Jan. 2005  4-17 
Switch-based interconnect architecture for future systems on chip  P. Pande    SPIE, VLSI Circuits and Systems; Volume 5117  May 2003  228-237 
A virtual channel network-on-chip for GT and BE traffic      ISVLSI; Vol 00  Mar. 2006   
Integration of a NOC-based multimedia processing platform  B. Ahmad, A. Erdogan, S. Khawam    FPL  Aug. 2005  606-611 
Interfacing cores with on-chip packet-switched networks  P. Bhojwani, R. Mahapatra    VLSI Design  Jan. 2003  382-387 
Designing message-dependent deadlock free net works on chips for application-specific systems-on-chips, in IFIP  S. Murali,P. Meloni,F. Angiolini,D. Atienza, S. Carta,L. Benini,L. Raffo, andG.deMicheli      2006   
Bringing NoCs to 65nm  A. Pullini,F. Angiolini,S. Murali D. Atienza, G. De Micheli, and L. Benini    Sep.-Oct 2007    IEEE Micro, vol.27, no.5, pp.75-85 
SoCIN: a Parametric and Scalable Network-on-Chip  C. A. Zeferino, A. A. Susin  16th Symposium on Integrated Circuits and Systems, 2003  Proceedings 16th Symposium on Integrated Circuits Systems 03  September 2003  169 - 174 
ParIS-A Parameterizable Interconnect Switch for Networks-on-Chip  C. A. Zeferino, F. G. M. Espirito Santo, A. A. Susin  17th Symposium on Integrated Circuits and Systems (SBCCI'04)  ACM Press  September 2004  pp.204-209 
BLACK-BUS: A New Data-Transfer Technique Using Local Address on Networks-on-Chip  K. Anjo, Y. Yamada, M. Koibuchi, A. Jouraku, H. Amano  18th IPDPS 2004  Proceedings, 18th IPDPS  April 26-30 2004  10-17 
Integrated Modeling and Generation of a Reconfigurable Network-on-Chip  D. Ching, P. Schaumont, I. Verbauwhede  18th IPDPS 2004  Proceedings, 18th IPDPS  April 26-30 2004  139-145 
Architecture of a dynamically reconfigurable noc for adaptive reconfigurable mpsoc  B. Ahmad, A. Erdogan, and S. Khawam  AHS    Jun. 2006  pp. 405411 
The design and implementation of a low-latency on-chip network  R. Mullins, A. West, S. Moore  ASP-DAC    Jan. 2006   
DyAD - smart routing for networks-on-chip  J. Hu, R. Marculescu  DAC    Jun. 2004  260-263 
A low latency router supporting adaptivity for on-chip interconnects  J. Kim, et al.  DAC    Jun. 2005  559-564 
Prediction-based Flow Control for Network-on-Chip Traffic,  U.Y Ogras, R. Marculescu  DAC, 2006    2006  pp. 839-844. 
SPIN: a scalable, packet switched, on-chip micro-network  A. Adriahantenaina  DATE    Mar. 2003  70-73 
A Router Architecture for Connection-Oriented Service Guarantees in the MANGO Clockless Network-  T. Bjerregaard and J. Sparsoe  DATE 2005    March 7-11, 2005  Vol.2 , pp. 1226-1231 
RASoC: A Router Soft-Core for Networks-on-Chip  C.A. Zeferino, M.E. Kreutz, A.A. Ssin  DATE, 2004  Proceedings, DATE 2004; Volume 3  February 16-20, 2004  198-203 
Guaranteed Bandwidth Using Looped Containers in Temporally Disjoint Networks Within the Nostrum NoCs  M. Millberg, E. Nilsson, R. Thid, A. jansch  DATE, 2004  Proceedings, DATE 2004; Volume 2  February 16-20, 2004  890-895 
A multi-path routing strategy with guaranteed in-order packet delivery and fault-tolerance for networks on chip  S. Murali, D. Atienza, L. Benini, G. De Micheli  Design Automation Conference (DAC), 2006    2006  pp. 845 – 848 
Network-on-chip for reconfigurable systems: From high-level design down to implementation  T. Bartic  FPL    2004  637-647 
A High-Speed and Lightweight On-Chip Crossbar Switch Scheduler for On-Chip Interconnection Networks  Kangmin Lee, Se-Joong Lee, Hoi-Jun Yoo  IEEE ESSCIRC 2004  Digest of Technical Papers, ESSCIRC 2003  Sept. 16-18, 2003  Pages: 453-456 
SILENT : Serialized Low Energy Transmission Coding for On-Chip Interconnection Networks  Kangmin Lee, Se-Joong Lee, Hoi-Jun Yoo  IEEE ICCAD 2004  Digest of Technical Papers, ICCAD 2004  Nov. 7-11, 2004  Pages: 448-451 
A High-Performance Router Design for VDSM NoCs  A. Narasimhan, K. Srinivasan, R. Sridhar  IEEE International SOC Conference    Sept. 25-28, 2005  pp. 301 - 304. 
On-Chip Network Based Embedded Core Testing  Jong-Sun Kim, Min-Su Hwang, Seungsu Roh, Ja-Young Lee, Kangmin Lee, Se-Joong Lee, Hoi-Jun Yoo  IEEE International SoC Conference (SOCC) 2004  Digest of Technical Papers, SOCC 2004  Sept. 12-15, 2004  Pages: 223-226 
Design of a Switch for Network on Chip Applications  P.P. Pande, C. Grecu, A. Ivanov, Res Saleh  IEEE ISCAS, 2003  ISCAS 2003 Volume: V  2003  217-220 
Network-on-chip architectures and design methods  L. Benini, D. Bertozzi  IEEE Proceedings on Computers and Digital Techniques    March 2005  Vol. 152, Iss. 2, pp. 261 - 272 
Network-on-chip architectures and design methods  L. Benini, D. Bertozzi  IEEE Proceedings on Computers and Digital Techniques  Volume 152, Issue 2  March 2005  pp. 261 - 272 
Highly Scalable Network on Chip for Reconfigurable Systems  T.A. Bartic, J-Y. Mignolet, V. Nollet, T. Marescaux, D. Verkest, S. Vernalde, R. Lauwereins  International Symposium on System-on-Chip, 2003  Proceedings, International Symposium on System-on-Chip, 2003  November 2003  79 - 82 
Buffer Implementation for Proteo Network-on-chip  I. Saastamoinen, M. Alho, J. Nurmi  ISCAS, 2003  Proceedings, ISCAS 2003 Volume: 2  May 25-28, 2003  II-113 - II-116 
A 51mW 1.6 GHz on-chip network forlow-powerheterogeneous SoC platform  K. Lee, S.-J. Lee, S.-E. Kim, H.-M. Choi, D. Kim, S. Kim, M.-W. Lee, and H.-J. Yoo  ISSCC,Feb.2004    Feb.2004  pp.152-158 
An Asynchronous NOC Architecture Providing Low Latency Service and Its Multi-Level Design Framework  E. Beigne, F. Clermidy, P. Vivet, A. Clouard, M. Renaudin  Proceedings of 11th IEEE International Symposium on Asynchronous Circuits and Systems    4-16 March 2005  pp. 54 - 63 
MultiNoC: A Multiprocessing System Enabled by a Network on Chip  A. Mello, L. Moller, N. Calazans, F.Moraes  Proceedings of Design, Automation and Test in Europe (DATE)    07-11 March 2005  pp. 234 - 23 
An Asynchronous Router for Multiple Service Levels Networks on Chip  D. Rostislav, V. Vishnyakov, E. Friedman, Ran Ginosar  Proceedings of IEEE International Symposium on Asynchronous Circuits and Systems(ASYNC)    14-16 March 2005  pp. 224-229 
Interfacing Cores with On-chip Packet-Switched Networks  P. Bhojwani, R. Mahapatra  Proceedings, IEEE VLSI Design  January 4-8, 2003  382 - 387  382 - 387 
A .13 um 1Gb/s/channel store-and-forward network-on-chip  F. Mondinelli, M. Borgatti, Z. Vajna  SOCC    Sep. 2004  141-142 
An asynchronous on-chip network router with quality-of-service (qos) support  F. Felicijan and S. Furber  SOCC    Sep. 2004  pp. 274277 
On-line reconfigurable extended generalized fat tree network-on-chip for multiprocessor soc circuits  H. Kariniemi  Tampere University of Technology Ph.D dissertation    Sep. 2006   

Sockets, Interfaces and Reuse

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Published
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Page(s)
Bridge over troubled wrappers:automated interface synthesis  V. D'silva, S. Ramesh, A. Sowmya    Proceedings. 17th International Conference on VLSI Design  2004  pp. 189- 194 
A Switch Wrapper Design for SNA On-Chip-Network,  J. Chang, J. Yi, J. Kim    Lecture Notes in Computer Science, Vol. 3740,  Oct. 2005,  405 - 414 
Open Core Protocol Specification, v2.0  OCP International Partnership (OCP-IP)      September 2003  210 pages 
Thermal-aware IP virtualization and placement for networks-on-chip architecture  W. Hung, C. Addo-Quaye, T. Theocharides, Y. Xie, N. Vijaykrishnan, M.J. Irwin    Proceedings of IEEE International Conference on Computer Des  11-13 Oct. 2004  pp. 430 - 437 
System-level Design: Orthogonalization of Concerns and Platform-based Design  K. Keutzer, A.R. Newton, J.M. Rabaey, A. Sangiovanni-Vincentelli    IEEE Transactions on Computer-Aided Design of Integrated Circuits; Volume: 19, Issue: 12  December 2000  1523-543 
Midbus Interface Functional Specification, v1.1  Altera Corporation      February 23, 2001  10 pages 
Effcient on-chip communications for data-flow IPs  A. Fraboulet, T. Risset    Proceedings. 15th IEEE International Conference on Applicati  27-29 Sept. 2004  pp. 293 - 303 
Open Microprocessors Systems Initiative, PI-Bus VHDL Toolkit Version 3.1  M. Bassett, P. Lister, University of Sussex    Open Micro-processor Systems Initiative (OMI) Concertation M  November 8-9, 1994   
Virtual Component Interface Standard  Virtual Socket Interface Alliance (VSIA)    OCB Specification 2, Version 1.0, 2000  2000   
AIRbus Interface Functional Specification, version 1.0  Altera Corporation    Document Identifier A-FS-09-01  December 22, 2000  8 pages 
Atlantic Interface Functional Specification, v3.0  Altera Corporation      June 2002  10 pages 
Reuse Methodology Manual: for System-on-a-Chip Designs  M. Keating, P. Bricaud    ISBN:0-7923-8175-0, Kluwer Academic Publishers Norwell, MA,  1998  224 
IP Interface Semiconductor Reuse Standard (SRS)  Motorola Inc.    SRS04IPI V2.0  1999  148 pages 
AHB-Lite overview  ARM Ltd.    ARM SDVI 0044A  2001  6 pages 
Open Core Protocol Specification v1.0  OCP International Partnership (OCP-IP)      September 2001  201 pages 
Surviving the SoC Revolution: A Guide to Platform-based Design  H. Chang, L. Cooke, M. Hunt, G. Martin, A.J. McNelly, L. Todd    Kluwer Academic Publishers, Norwell, MA, USA  1999   
Experiments with the Peripheral Virtual Component Interface  R.L. Lysecky, F. Vahid, T.D. Givargis  13th International Symposium on System Synthesis (ISSS) 2000  Proceedings, 13th ISSS 2000  September 20-22, 2000  221-224 
IP Reuse in the System-on-Chip Era  W. Savage, J. Chilton, R. Camposano  13th International Symposium on System Synthesis (ISSS) 2000  Proceedings, 13th ISSS 2000  September 20-22, 2000  2-7 
An Approach to PVCI-based Wrapper Design  S. Zhang, M. Gao, Y. Hu, L. Li  5th International Conference on ASIC  Proceedings, 5th International Conference on ASIC Volume: 1  October 2003  433-437 
Comprehensive Interconnect BIST Methodology for Virtual Socket Interface  Chauchin Su; Yue-Tsung Chen  7th Asian Test Symposium (AST) 1998  Proceedings AST 1998  December 2-4, 1998  259-263 
Essential Issues for IP Reuse  D. Gajski, A.C.-H Wu, V. Chaiyakul, S. Mori, T. Nukiyama, P. Bricaud  Asia & S. Pacific Design Automation Conference ASP-DAC 2000  Proceedings ASP-DAC 2000  January 25-28, 2000  37-42 
VSIA: It's Advantages from Four Different Perspectives  L.H. Cooke  Custom Integrated Circuits Conference (CICC) 1997  Proceedings CICC 1997  May 5-8, 1997  107-111 
Design of a Virtual Component Neutral Network-on-Chip Transaction Layer  Philippe Martin  DATE 2005    2005  336-337 
Interface-based Design  J.A.. Rowson, A Sangiovanni-Vincentella  Design Automation Conference (DAC) 1997  Proceedings DAC 1997  June 9-13, 1997  178-183 
An efficient scalable and flexible data transfer architecture for multiprocessor SoC with massive...  Sang-Il Han, Amer Baghdadi, Marius Bonaciu, Soo-Ik Chae, Ahmed A. Jerraya,  Design Automation Conference archive (DAC)    June 07 - 11, 2004  250 - 255. 
Standards for System-level Design: Practical Reality or Solution in Search of a Question?  C.K. Lennard, P. Schaumont, G. de Jong, A. Haverinen, P. Hardee  Design, Automation and Test in Europe (DATE) 2000  Proceedings, DATE 2000  March 27-30, 2000  576-583 
Applying the OpenMORE Assessment Program for IP Cores  J.-P. Gueguen, P. Bricaud  First ISQED  Proceedings ISQED 2000  March 20-22, 2000  379-381 
IP Reuse Creation for System-on-a-Chip Design  P. Bricaud  IEEE Custom Integrated Circuits Conference (CICC) 1999  Proceedings CICC 1999  1999  395-401 
VSIA Technical Challenges  H. Sachs, M. Birnbaum  IEEE Custom Integrated Circuits Conference 1999  Proceedings CICC 1999  May 16-19, 1999  619-622 
AMBA: Enabling Reusable On-Chip Designs  D. Flynn  IEEE Micro  Volume: 17, Issue 4  July-August 1997  20-27 
Comparison of Hardware IP Components for System-on-Chip  E. Salminen, K. Kuusilinna, T.D. Hamalainen  International Symposium on System-on-Chip    November 16-18, 2004  69-73 
An OCP Compliant Network Adapter for GALS-based SoC Design Using the MANGO Network-on-Chip  Bjerregaard, S. Mahadevan, R.G. Olsen, J. Sparsoe  International Symposium on System-on-Chip, 15-17 Nov. 2005  Tampere, Finland  2005  171 - 174 
Testing Reusable IP: A Case Study  P. Harrod  International Test Conference (ITC) 1999  Proceedings, ITC 1999  September 28-30, 1999  148 pages 
Enabling Reuse via an IP Core-centric Communications Protocol: Open Core Protocol  W.-D. Weber  IP 2000 System-on-Chip Conference  Proceedings, IP 2000 System-on-Chip Conference  March 20-22, 2000   
VSIA Quality Metrics for IP and SoC  M. Birnbaum, C.C. Johnson  ISQED 2001  Proceedings on ISQED 2001  March 26-28, 2001  279-283 
MicroNetworks for Flexible SoC Platforms  D. Wingard  Sophia Antipolis Forum on MicroElectronics (SAME) 2000  Proceedings, SAME 2000  October 2000   

Wiring Problem

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Title
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Published
Date
Page(s)
Reducing interconnect cost in NoC through serialized asynchronous links in NOCS   S. Ogg, E. Valli,C.D Alessandro, A. Yakovlev, B. Al-Hashimi, and L.Benini      May 2007  pp.219-219 
System design of full HD MVC decoding on mesh-based multicore NoCs. Microprocessors and Microsystems - Embedded Hardware Design  Ning Ma, Zhonghai Lu, Li-Rong Zheng      March 2011  Embedded Hardware Design 35(2): 217-229 
Buffer Optimization in Network-on-Chip Through Flow Regulation  Fahimeh Jafari, Zhonghai Lu, Axel Jantsch, and Mohammad Hossein Yaghmaee      December 2010  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD). 29(12), pages 1973 - 1986 
Analysis of Worst-Case Delay Bounds for On-Chip Packet-Switching Networks  Yue Qian, Zhonghai Lu and Wenhua Dou      May 2010  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 29(5), pages 802 - 815 
TDM Virtual-Circuit Configuration for Network-on-Chip  Zhonghai Lu and Axel Jantsch      August, 2008  IEEE Transactions on Very Large Scale Integration Systems (TVLSI), 16(8):1021-1034 
Admitting and Ejecting Flits in Wormhole-switched Networks on Chip  Zhonghai Lu and Axel Jantsch      September 2007  IET Computers & Digital Techniques 1(5):546-556 
Cross Clock-Domain TDM Virtual Circuits for Networks on Chips  Zhonghai Lu  ACM/IEEE International Symposium on Networks-on-Chip (NoCS'2011)    May 2011   
Getting to the Bottom of Deep Submicron  D. Sylvester, K. Keutzer  IEEE/ACM ICCAD, 1998  Digest of Technical Papers, ICCAD 1998  November 8-12, 1998  203 - 211 
Impact of small process geometries on microarchitectures in systems on a chip  D. Sylvester, K. Keutzer  Proceedings of the IEEE  Volume 89, Issue 4  April 2001  pp. 467 - 489 
The future of wires  R. Ho, K.W. Mai, M.A. Horowitz  Proceedings of the IEEE  Volume 89, Issue 4  April 2001  pp. 490 - 504 
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