OCP Compliant EDA Products
Provider
Description
Available Services
Contact
Magillem Design Services  Magillem helps companies to implement IP-XACT: Semiconductor manufacturers: migration of the database and the design flow EDA vendors: IP-XACT layer of the tools interfaces IP providers: IP metadata description and configuration nutshell Magillem audit the existing industrial flow and propose a work plan to adapt engineers to IP-XACT. We assess and verify the full compatibility of tools interfaces into a flow testbench. Magillem tests the IP deliverables against a benchmark using its IP-XACT PACKAGER and check IP integration properties onto a test system. Geday
+33.1.40.21.35.50
geday@magillem.com 
YogiTech  Flexibility and configurability are main features of OCP and they represent the main challenge for design and verification of OCP interfaces. Moreover IP validation can be very time consuming if not supported by expert verification engineers and powerful and efficient methodology. YogiTech's relevant experience in design and verification of OCP-based subsystem and modules, along with the adoption of Specman Elite and OCP 2.0 eVC can guarantee high quality products and effective time-to-market. Design and integration of OCP bridges and interfaces, verification plan drafting, verification of OCP-based systems and modules, and development of customized verification environment based on Specman Elite methodology. Natale Barsotti
natale.barsotti@yogitech.com 
Sonics, Inc.  Sonics, Inc. is a premier developer of smart intellectual property (IP) products that dramatically accelerate complex SoC design times while minimizing risk. The Sonics Methodology and Architecture for Rapid Time-to market (SMART ) initiative is a comprehensive collection of products, services and partnerships to ensure customers successfully develop more capable devices with lower power consumption and lower cost while achieving more SoC complexity faster. Check Web site Stephen Tomasello
408-474-2800
stephen@sonicsinc.com 
Duolog  Duolog offers professional flow automation services that are tailored to customer-specific requirements. The solutions are developed based on our flexible Socrates tool suite and complement major third-party EDA tools suites. Duolog offers testbench automation services, IP Packaging to facilate automated system integration and expertise on SOC design flow methodologies. Our flow automation expertise includes the creation of flows such as automatic generation of testbenches for SystemVerilog, UVM & OVM, ‘e’/Specman, SystemC. Our customers use our design services team to create IP, subsystem and system level testbenches for OCP based SOC architectures. We can enhance customers IP packaging to faciliate efficient and reusable IP integration at both the RTL and TLM levels of abstraction. We can provided pre-configured integration rules to handle the integration of OCP-IP. Examples of our experience include IP packaging for top mobile processor provider and the development of a unified AMS verification flow based on SystemVerilog UVM for a multi-billion USD analog semiconductor company. +353-1-2178400
support@duolog.com 
Verilab  The Verilab OCP uVC is a mixed language verification component for the Open Core Protocol (OCP) implemented using SystemVerilog and e verification languages. It can be used as an Open Verification Methodology (OVM) Verification Component (OVC) in SystemVerilog-only applications without the Specman layer (or license), or it can be used in Specman-based verification environments as a regular e Verification Component (eVC). Verilab is an elite international team of consultants providing expertise in architecting and implementing verification environments for many applications including OCP-based System-on-Chip (SoC) and module-level IP. We developed the OCP uVC as a more robust, cost-effective and portable verification component for use in multi-vendor simulation environments with the full capability of an eRM compliant eVC in Specman-based environments and yet providing a direct or migration path to SystemVerilog-only OVM compliant verification environments. Verilab can port existing environments to make full use of the OCP uVC, architect and implement new solutions from the ground up, or work effectively with existing architectures to ensure verification success in your next OCP project. Mark Litterick
ocp_info@verilab.com 
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ASIC
Part #
Description
Company Name
Contact
F3000  0.13 eASIC Corporation  Sales.Support
408-879- 9400
info@easic.com 
FA1000  0.13 eASIC Corporation  Sales.Support
408-879- 9400
info@easic.com 
F3000  0.13 eASIC Corporation  Sales.Support
408-879- 9400
info@easic.com 
FA1000  0.13 eASIC Corporation  Sales.Support
408-879- 9400
info@easic.com 
F3000  0.13 Structured ASIC. 3000K ASIC Gates, 5.8Mbits Memory, 8 PLLs, 800 I/O eASIC Corporation  Sales.Support
408-879- 9400
info@easic.com 
F2000  0.13m Structured ASIC. 2000K ASIC Gates, 2.9 Mbits Memory, 8 PLLs, 650 I/O eASIC Corporation  Sales.Support
408-879- 9400
info@easic.com 
F2000  0.13m Structured ASIC. 2000K ASIC Gates, 2.9 Mbits Memory, 8 PLLs, 650 I/O eASIC Corporation  Sales.Support
408-879- 9400
info@easic.com 
FA250L  0.13m Structured ASIC. 250K ASIC Gates, 256Kbits Memory, 1 PLL, 150 I/O eASIC Corporation  Sales.Support
408-879- 9400
info@easic.com 
FA250L  0.13m Structured ASIC. 250K ASIC Gates, 256Kbits Memory, 1 PLL, 150 I/O eASIC Corporation  Sales.Support
408-879- 9400
info@easic.com 
FA250L  0.13m Structured ASIC. 250K ASIC Gates, 256Kbits Memory, 1 PLL, 150 I/O eASIC Corporation  Sales.Support
408-879- 9400
info@easic.com 
FA250  0.13m Structured ASIC. 250K ASIC Gates, 448Kbits Memory, 2 PLLs, 150 I/O eASIC Corporation  Sales.Support
408-879- 9400
info@easic.com 
FA250  0.13m Structured ASIC. 250K ASIC Gates, 448Kbits Memory, 2 PLLs, 150 I/O eASIC Corporation  Sales.Support
408-879- 9400
info@easic.com 
FA250  0.13m Structured ASIC. 250K ASIC Gates, 448Kbits Memory, 2 PLLs, 150 I/O eASIC Corporation  Sales.Support
408-879- 9400
info@easic.com 
FA600  0.13m Structured ASIC. 600K ASIC Gates, 1Mbits Memory, 4 PLLs, 350 I/O eASIC Corporation  Sales.Support
408-879- 9400
info@easic.com 
FA600  0.13m Structured ASIC. 600K ASIC Gates, 1Mbits Memory, 4 PLLs, 350 I/O eASIC Corporation  Sales.Support
408-879- 9400
info@easic.com 
FA600  0.13m Structured ASIC. 600K ASIC Gates, 1Mbits Memory, 4 PLLs, 350 I/O eASIC Corporation  Sales.Support
408-879- 9400
info@easic.com 
T6TC1XB-0001  ARM926 Network Controller Toshiba  Steve Williams
408-404-6751
steve.williams@glb.toshiba.co.jp 
T6TC1XB-0001  ARM926 Network Controller Toshiba  Steve Williams
408-404-6751
steve.williams@glb.toshiba.co.jp 
T6TC1XB-0001  ARM926 Network Controller Toshiba  Steve Williams
408-404-6751
steve.williams@glb.toshiba.co.jp 
Duolog  Duolog offers professional flow automation services that are tailored to customer-specific requirements. The solutions are developed based on our flexible Socrates tool suite and complement major third-party EDA tools suites. Duolog offers testbench automation services, IP Packaging to facilate automated system integration and expertise on SOC design flow methodologies.   +353-1-2178400
support@duolog.com 
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