Accellera’s UVM in SystemC Standardization: Going Universal for ESL
by Adam Sherer, Accellera Promotions Committee Chair
Reusable, modular, and scalable testbenches based on the Accellera Universal Verification Methodology (UVM) standard are used throughout the electronics industry. Thousands of engineers have used phasing, factory, configuration, reporting, and other features of the SystemVerilog-based reference implementation class library supplied by Accellera to build UVM verification components (UVC). Since these UVCs include automated stimulus generation, independent results generation, and coverage collection, many project teams are now able to implement coverage-driven verification (CDV) methodologies. Altogether, UVM is a great success bringing both reuse and improved overall verification efficiency primarily for RTL IP design.
However, electronic system level (ESL) design lacks a similar verification standard. This issue is becoming more important as complex system on chip (SoC) projects increasingly depend on ESL. Ad hoc methods have been used with the premise that ESL design is modeled in SystemC/C++ and the RTL is modeled separately in SystemVerilog/VHDL. As project teams use high-level synthesis (HLS) and manual methods, the models are mixed in simulation making the ad hoc methods inefficient. The SystemVerilog-based UVM reference library could be used, but ESL designs are typically verified using SystemC/C++ for both the hardware and embedded software models running in the complete SoC. Therefore, ESL verification engineers prefer a reference implementation of UVM in SystemC. This would simplify communication between these layers of design abstraction and enable parallel verification development furthering the goal of raising overall verification efficiency.
In September 2011, a European project that was part of the 7th Framework Program was established to port UVM to SystemC. Known as the Verification for Heterogeneous Reliable Design and Integration (VERDI), the main objective was the development of a unified system-level verification methodology for heterogeneous systems. The VERDI partners included Fraunhofer, NXP, Infineon, Continental, Magillem, and UPMC. Working together for three years, the VERDI project concluded in October 2014 with a contribution of a language reference manual (LRM) and a reference implementation to Accellera for further standardization.
The contribution was made to the Accellera SystemC Verification Working Group (VWG). It is primarily based on UVM 1.1 with identical class definitions and method signatures wherever possible. The reference implementation is based on the ISO/IEC 14882-2003 (C++03) and IEEE Std 1666-2011 (SystemC) standards and is supported by a well-documented API and LRM. Both the LRM and the reference implementation are provided under the Apache 2.0 license.
The UVM-SystemC library currently provides the classes and methods needed to build SystemC-based testbenches as shown in the table. The component classes are used to build the agents, sequences, drivers, etc. that comprise UVCs. These UVCs are connected into testbenches with test and virtual sequences. For reuse, the configuration and factory mechanisms are available. Simulation control is provided through phasing and objection handling. Finally, print, compare, messaging, etc. are provided for data management and debugging. A register abstraction layer and coverage groups are in development while constrained randomization is in discussion with the Accellera SCV standard and a supplemental constraint solver (CRAVE) as possible solutions.
UVM in SystemC is now being reviewed and enhanced in the Accellera VWG. The development work starts with a detailed review of the LRM and the identification of needed changes and improvements. In parallel, these are coded into the reference implementation to validate the LRM. The VWG is working toward a public draft of UVM-SystemC later in 2015 including both the LRM and the reference implementation.
Looking forward, there is much more to be done. Since the UVM working group released UVM 1.2 in SystemVerilog, the VWG is also discussing how to make UVM SystemC compatible with this newer version. The VWG is also discussing how to add constrained random and functional coverage features as well as compatibility with the multi-language verification framework also under development in Accellera. This is an exciting time for ESL design and verification. If your company is an Accellera member, join the VWG to help create this standard and/or participate in the public review later this year. Either way, your contributions will extend the efficiency of UVM to a whole new abstraction for embedded system and SoC verification: UVM will become truly universal.
Adam Sherer is chair of the Accellera Promotions Committee