Tutorial: SystemVerilog-AMS: The Future of Analog/Mixed-Signal Modeling
Presented at DVCon U.S. 2016 on February 29, 2016
In the 2012 revision of SystemVerilog, nettypes and interconnect were added to provide language features for modeling analog/mixed-signal (AMS) circuits. While these constructs are useful, they do not provide a complete solution for those interested in complex AMS modeling scenarios. Verilog-AMS is a much more complete AMS modeling solution, but it is based on the Verilog IEEE Std 1364-2005 standard which has been superseded by SystemVerilog.
Over the past two years, a small group of Verilog-AMS and SystemVerilog experts have been meeting with the goal of unifying SystemVerilog and Verilog-AMS. This tutorial provides an introduction to the concepts underlying the upcoming SystemVerilog-AMS language standard.
Martin Vlach, Mentor Graphics
Scott Little, Intel