Tutorial: Focusing on High-Level Synthesis and Functional Coverage for SystemC
Presented at DVCon U.S. 2019 on February 25, 2019
This tutorial provides an overview on High Level Synthesis (HLS) with a discussion on data types and model structure as well as lessons learned. It also includes Functional Coverage for SystemC and a brief update on the Accellera SystemC Working Group.
The tutorial is split into five sections:
- Part 1: High-Level Synthesis with SystemC: An Introduction
Fred Doucet, Facebook
Writing a hardware design in SystemC model and using High-level Synthesis (HLS) to synthesize it to a register transfer level (RTL) model can yield many significant productivity benefits when compared to traditional RTL design flows. In this talk, we describe the fundamental structures of a SystemC design model and what is abstracted in a SystemC model that is explicit in an RTL model. We then show how HLS tools are be used to concretize the abstraction into the desired structures in the RTL model, the productivity benefits and the remaining challenges in typical HLS flows.
- Part 2: High-Level Synthesis: Model Structure and Data Types
Mike Meredith, Cadence
SystemC models used as input for synthesis must be properly structured. They differ in important ways from models used for virtual platform development and other purposes. Differences include restrictions in the C++ and SystemC constructs that can be used and a much greater use of SystemC bit-accurate datatypes and fixed-point datatypes. The issues surrounding model structure and data types for synthesis are discussed in this section.
- Part 3: High-Level Synthesis: Lessons Learned - Intel's Experience
Bob Condon, Intel
SystemC HLS usage has matured, and product teams have used it for multiple generations of designs. In this section, we present some lessons learned in wide-scale deployment including some techniques for triaging HLS errors, how HLS fits in power flows, and techniques repurposed from the software engineering world to make code easier to maintain over multiple generations.
- Part 4: Functional Coverage for SystemC (FC4SC)
Dragos Dospinescu, AMIQ
Functional coverage lies at the core of functional verification as the primary metric that assesses the quality of the entire verification process. This notion of functional coverage can be extended from the scope of RTL verification to the verification of any type of application. The Functional Coverage for SystemC (FC4SC) is a header-only library that provides mechanisms for functional coverage definition, collection and reporting that can be used in any application which is compliant with the C++ standard, starting with C++11. In this section, we provide an introduction into FC4SC's capabilities, accompanied by examples of how to use the library for constructing and managing your coverage model.
- Part 5: Accellera SystemC Working Group Update
Martin Barnasconi, NXP
A number of activities are currently underway within the Accellera technical working groups that are of interest to the SystemC community. This section provides a brief update on some of the activities of these working groups.