Community Newsletter: December 2014
IN THIS ISSUE:
- DVCon is Global
Adam Sherer talks DVCon expansion
- DVCon Europe Attendees: "First-time-right"
Martin Barnasconi reports on the first DVCon Europe
- DVCon India: An Exhibitor's Story
The DVCon India conference from an exhibitor's point of view
- Upcoming: DVCon United States
March 2-5, San Jose, California
- Complete Set of Technical Tutorials from DVCon Available
UPF, SystemC, SystemC AMS, OCP, and UVM
by Adam Sherer, Accellera Promotions Committee Chair
Success! You all proved that the attributes that make DVCon United States a hit — deep technical content presented by experts to an expert audience — are globally appealing. Together, we launched the DVCon India and the DVCon Europe this year. The peer-reviewed technical sessions were the foundation for both and the keynote presentations provided a regional focus for each event. The result was attendance that exceeded expectations. Thank you!
Now, on to DVCon 2015. We’ll kick-off the DVCon year with DVCon United States in first week of March. Of course, we will return to India and Europe in the fall. Throughout the year we will be exploring other regions as well to understand how and when to bring DVCon to you. DVCon is by engineers and for engineers. Whether you attend to learn, submit an abstract to share, or staff a panel to guide the future take part in DVCon to help our industry grow!
by Martin Barnasconi, General Chair, DVCon Europe 2014
The first DVCon in Europe was a big success. More than 200 design and verification engineers from across Europe visited Munich in Germany. Most of the attendees (75%) came from Germany, United Kingdom, The Netherlands, France and the United States. In addition, engineers from Austria, Belgium, Denmark, Israel and Sweden attended this new event.
The 14 tutorials, a poster session and technical sessions on various design and verification topics were well attended; in some cases the rooms were too small to offer seating for everyone! In addition, DVCon Europe hosted a vibrant exhibition with 19 exhibitors offering training, consultancy, EDA design solutions or IP services. During the prime time exhibition hours, we clearly had a "full house." It was great to see so many people interacting with the exhibitors and other experts on sharing design and verification experiences. Many attendees called DVCon Europe a "first-time-right" event in Europe.
Knowing that also other companies would have liked to exhibit or attend DVCon Europe, we clearly need more space for DVCon Europe in the future. And with the successful event and experiences of DVCon Europe 2014, Accellera has already started exploring options to host DVCon Europe at a bigger venue in 2015. So watch for Accellera or DVCon Europe newsletters in the coming months — and mark your calendar to visit DVCon Europe in Autumn 2015!
by Anupam Bakshi, Finance Chair, DVCon India 2014
Until August 2014, when you told someone you are attending DVCon, it was assumed you were talking about DVCon United States held each year at DoubleTree in San Jose. Well, this September that changed. Now when you talk about DVCon, you will have to specify where in the world you are talking about, thanks to the new DVCon events in India and Europe!
As the only emerging company that exhibited at all three DVCon events in 2014, it was important for Agnisys to go to India and Europe along with the US. Interacting with the large local community helped us understand the latent needs of the local engineer — their hot buttons and their roadblocks to productivity. It also helped us identify which ideas and features in our products resonated with the engineers. This has helped us give a direction and a roadmap to our products. For example, we decided to add a feature called Automatic Register Verification when we found, anecdotally, that often verification engineers spend 70% of their working time on register map related tests and verification infrastructure. We were quick to add this capability in IDesignSpec. This shows the power of attending such conferences, which should be called KYC — Know Your Customer — events!
The other aspect of such a conference is to interact with the innovators and great minds of the industry. In India and Europe the technical content was varied and casted a wide net. Under one roof, our engineers quickly came up to speed on a whole variety of emerging technology — the latest in UVM, portable stimulus, UPF, UVM-SystemC, etc.
We plan to exhibit at all DVCon exhibits in 2015. Read our articles for the three events on our company blog site using these links.
- Blog Post on DVCon United States
- Blog Post on DVCon India, Organizing DVCon India
- Blog Post on DVCon Europe
DVCon United States is fast approaching! The conference experienced record numbers in attendance and exhibitors in 2014, with close to 1200 participants. There were 41 exhibitors, including 15 first-timers and 10 international companies. Check out the videos from the 2014 tutorials. So mark your calendar! And in the meantime, here are some highlights for 2015:
- DVCon 2015 will be held March 2-5 at the Doubletree Hotel in San Jose, California.
- Accellera Day will help put the design back into the Design and Verification Conference with sessions on SystemVerilog design, SystemC design, low power, and more.
- The Accellera Day luncheon topic will focus on "What is Needed to Drive Design Efficiency?"
- The Tuesday keynote address by Aart De Geus of Synopsys will highlight "Smart Design, from Silicon to Software"
- Wednesday panels topics, "Art or Science" and "SystemC — Forever a Niche Player or Rising Star of Chip Design?" will give attendees much to discuss during the conference.
- The Booth Crawl reception on Monday evening and Exhibits Reception on Tuesday and Wednesday evenings during the conference provide an excellent opportunity for attendees to network.
- Advance Registration is now open.
Sign up here to attend the DVCon US 2015 conference.
The complete set of technical tutorials from Accellera Day at DVCon 2014 is now available:
- Using UPF for Low Power Design and Verification presents the latest information on the Unified Power Format (UPF). Beginning with a review of the concepts, terminology, commands, and options provided by UPF, it covers the full spectrum of UPF capabilities and methodology, from basic flows through advanced applications, with particular focus on incremental adoption of UPF.
- In Case Studies in SystemC, hands-on users and tool developers share their recent experience and describe advanced methodologies that have helped them achieve significant benefits. Includes a few of the most useful features introduced with SystemC 2.3.0 and code examples.
- OCP: The Journey Continues presents the past, present and future of the Open Core Protocol IP interface socket standard, which was transferred to Accellera in October, 2013. It includes a discussion about the future needs in IP core interfacing and where future version of the OCP standard may play a role.
- Experience the Next ~Wave~ of Analog and Digital Signal Processing using SystemC AMS 2.0 is a highly technical tutorial that targets system engineers, integrators, architects and verification engineers active in industrial projects where analog and digital signal processing functionality comes together and where interoperability between mixed-signal and HW/SW subsystems becomes apparent.
- UVM — What's Now and What's Next presents topics on sequence creation, register layer use (both beginner and advanced), TLM-based communication, test execution using run-time phases, and messaging enhancements.
In addition, The Future of Mixed Signal Verification: From Manual Simulations to Full Regression presents a panel discussion of emerging techniques that would enable the digital-centric mixed-signal community to reach their next level of verification. Moderated by Helene Thibieroz of Synopsys, the discussion includes panelists from Intel, Texas Instruments, Maxim Integrated, and Qualcomm.
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