Community Newsletter: May 2021
IN THIS ISSUE:
- Message from the Chair
- Tremendous Progress and Growth Continue Within Accellera
- News from our Working Groups
- PSS 2.0 Now Available for Download
- SA-EDI Public Review through May 21
- Functional Safety White Paper Now Available
- Upcoming Accellera Events in 2021
- DVCon China 2021
- “Remote Work, Remote Chip Design: Building Chips During a Pandemic” Panel co-sponsored with ESD Alliance/Semi
- SystemC Quarterly Fika Events
- Virtual DVCon Europe 2021
- Virtual SystemC Evolution Day
- Virtual DVCon India 2021
- DVCon U.S. 2021 Accellera Videos Available
- IEEE Get Program Update
Message from the Chair
Although many countries continue to face quarantine, fortunately the pandemic has not slowed progress or growth within Accellera. Just in the past few months we have eight new Associate Members and four new Start-up/University Members. We have also seen tremendous international expansion in our membership, with six new members coming from Europe and two from China.
Our working groups continue to make great progress in new standards development as well as advancing existing standards. We’ve just released the much-anticipated Portable Test and Stimulus Standard 2.0. The Portable Stimulus Working Group is comprised of many volunteer members across many companies whose hard work and dedication has come to fruition. This new industry standard for system-level verification brings exciting new capabilities to the engineering community to help them address ever-increasing complexities in design.
Our IP Security Assurance Working Group recently released its first draft standard for public review and our Functional Safety and UVM-AMS Working Groups have whitepapers coming soon. We encourage you to participate in the public review and go through the whitepapers and give your feedback. The way to make standards most beneficial is to provide honest and detailed critiques throughout the review process.
It is also encouraging to see some parts of the world begin to open to in-person events. Our DVCon China conference is going to be held in-person for the local community at the end of the month. And, if all continues to go well in the United States, DAC will be back with a combination of an in-person and virtual conference at the end of the year. Our other conferences, DVCon Europe and DVCon India, will continue to be virtual this year.
Meanwhile, we have created some interesting new online events. The first SystemC Evolution Fika was held in March and will continue quarterly to increase collaboration among the SystemC community. Participation in the first fika highlighted the many positive aspects of the virtual work environment—that we are connected across the globe and can come together easily online to share our thoughts and make things happen. We also have an online panel coming up in June that we are co-sponsoring with ESD Alliance/Semi that will focus on how engineers are building chips while working from home during the pandemic.
We hope you will join us for our events, participate in our working group activities, and continue to provide feedback to our ongoing standards efforts. Get involved and help develop the standards the way you would like them to be.
Lu Dai, Accellera Systems Initiative Chair
News from our Working Groups
Portable Test and Stimulus Standard 2.0 Now Available!
The Portable Test and Stimulus Standard (PSS) 2.0 is now available for download. New major features improve the usability of the PSS 2.0 standard, expanding its portability and flexibility to a broader class of verification challenges.
Additions to the 2.0 standard include several new language features:
- Core library for standard portable functionality and utilities for common PSS applications, including register accesses and memory allocation and management
- Core library for mapping scenario elements to execution agents in the target implementation
- Collection types, including arrays, lists, maps, and sets
- Parameterized types
- Constraint enhancements, including default constraints and propagation
- Enhanced activity-level generation and scheduling constructs
- Improved portability of procedural constructs for test realization
- Clarified rules for name resolution and conditional code processing for compilation
“The Portable Test and Stimulus Standard continues to enjoy great participation from design companies and committed support from a broad set of EDA suppliers. We are grateful for the significant volunteer contributions and proud of the mature capabilities the working group members produced in 2.0 while operating in a global pandemic environment,” stated Faris Khundakjie, Chair of the Portable Stimulus Working Group. “We are hopeful the user community will enjoy leaps of flexibility and practical applications with the newly added features. As always we continue to encourage our user community to influence this standard to foster continued success and adoption.”
Download the standard and release notes here.
For more information and resources, including a tutorial presented at virtual DVCon U.S. 2021, visit the Portable Stimulus Working Group Page here.
IP Security Assurance Draft Standard in Public Review
The Security Annotation for Electronic Design Integration (SA-EDI) Draft Standard 1.0 is available from the IP Security Assurance Working Group for public review through May 21, 2021.
The SA-EDI draft standard was developed by the working group to address security concerns for hardware and software IP in a manner that is low-overhead, non-disruptive, and scalable across multiple target implementations. It specifies an approach to provide information about the security properties of IP; this information is relevant to the integrator and provides recommended solutions to address risks. The working group’s focus is on utilizing existing standards that pertain to IP specification, design, verification, and integration where security risk is a concern, as well as known security concerns that have been identified by either industry experience or security researchers.
The objectives of the SA-EDI standard include:
- Offering IP providers a standardized means to disclose relevant security properties to consider in integration
- Assisting IP integrators in understanding and reducing security risk
- Accelerating tool development to facilitate security assurance automation
Download the draft standard here. The IP Security Assurance Working Group invites and encourages the community to participate in the review and provide feedback through Accellera’s SA-EDI Standard Discussion Forum.
For more information and additional resources, including a recording from a workshop presented at DVCon U.S. 2021, visit the IP Security Assurance Working Group page.
White Paper from Functional Safety Working Group Now Available!
The Functional Safety (FS) Working Group recently released its white paper that describes its initial proposal to develop a standard that will provide a definition of FS data exchange to improve automation, interoperability, traceability, and retargeting.
FS data is intended as the set of data needed to perform safety activities and to generate work products. The standard will specify a data model, language, or format to exchange data seamlessly.
The white paper details the challenges gathered by the Functional Safety Working Group and its mission, as well as provides insights into the role of the emerging standard into the standardization landscape and the strategy for its development. Additional goals for the working group and topics for future exploration are also addressed in the white paper.
View and download the white paper.
If you’d like to participate in the development of the Functional Safety standard and are not already a member of Accellera, we encourage you to join and help influence the ongoing efforts.
Upcoming Accellera Events in 2021
DVCon China 2021
DVCon China 2021 will be held on May 26th at the Renaissance Shanghai Pudong Hotel for local attendees.
The opening ceremony will be followed by two keynotes in the morning: “Computational Logistics for Intelligent System Design” presented by Simon Chang, Cadence Design Systems and “Next Generation of EDA” presented by Luke Yang, X-Epic Corporation.
There will be eight paper sessions, a poster session, and eight short workshops throughout the day. To view the program and register to attend, visit the conference website.
Panel: “Remote Work, Remote Chip Design: Building Chips During a Pandemic”
Mark your calendars for this timely Accellera and ESD Alliance/Semi co-sponsored live, interactive online panel on June 9 from 9-10am PT. Chip design verification engineers, accustomed to having a range of robust software and hardware resources readily available within their physical office environment, are faced with new limitations working from home. Their complicated and well-choreographed verification flows and project cycles may have taken a hit given VPN tool and system access, Zoom-based team collaboration, and necessary deep thinking interrupted with everyday home activities.
Nonetheless, verification hasn’t stopped through the pandemic. The panel will outline a set of best practices for chip design and verification engineers as they continue working from home, as well as the challenges of eventually getting back to the office.
- Martin Barnasconi, Technical Director System Design & Verification Methodologies, NXP
- Lu Dai, Senior Director of Engineering, Qualcomm
- Dr. Ashish Darbari, CEO, Axiomise
- Mark Glasser, Member of the Technical Staff, Cerebras
- Patrick Lynch, Senior Engineering Manager, Xilinx
The panel is free, but registration is required. For more information and to register, visit here.
The SystemC Evolution Continues with Quarterly Fika Events
The second SystemC Evolution Fika will be held June 30, 2021. There will be presentations on SystemC and QEMU from GreenSocs as well as a panel focused on SystemC Modeling Libraries. For more information, visit the SystemC Fika page. All are welcome to attend this free online event, but registration is required.
The first virtual SystemC Evolution Fika was held in March with approximately 80 in attendance for the two-hour workshop. There were two presentations, one focused on SystemC and Python and the other on the Intel SystemC Compiler. To view presentations from the previous fika and read a summary by Ola Dahl, Chair of SystemC Evolution Day, visit here.
Virtual DVCon Europe 2021
Letter from Sumit Jha, DVCon Europe 2021 General Chair
A warm welcome to DVCon Europe 2021!
First, I hope that you and your loved ones are doing well and that all of you are in good health.
In this COVID era, we have realized a new set of problems and opportunities which need to be addressed. Our generation is witnessing the steepest technological growth ever seen and innovations and modern gadgets are more of a necessity today than a luxury. This moment in time really validates the need and the importance of semiconductor technology and how that allows us to be in a much more connected world and enable completely new use cases.
And what this means is that the complexity of chip design and verification challenges are growing exponentially in the semiconductor industry. To keep us synced to the demand of advanced methodologies, tools, and techniques, we understand that DVCon Europe has a special responsibility. Especially when most of our peers are working from a home office with little opportunity to share ideas.
The Design and Verification Conference and Exhibition provides attendees around the globe with the industry’s most comprehensive technical program focused on the design and verification of electronic systems. It is also that time of the year when we celebrate, promote, and reward some of the brilliant ideas from the authors who are carefully shortlisted from the hundreds of submissions. We also get an opportunity to hear from industry leaders in the form of keynotes and panel sessions.
DVCon Europe, together with Accellera’s co-located SystemC Evolution Day, is all set to provide an extraordinary stage to showcase the finest innovative ideas, use cases, methodologies, languages, and standards that are helping you today and going to help our engineering community tomorrow. You will also get an insight to the latest Accellera activities, standards, and working groups.
Given the current scenario and uncertainty in terms of COVID variants and vaccinations, we are happy to organize this eighth edition of DVCon Europe as a virtual conference and exhibition. This year we plan to have more improvements and advancements in the 3D virtual experience. As always, we will have technical paper presentation, tutorials, panel, and keynotes, with the same spirit of organizing this prestigious conference for the users by the users.
Mark your calendar: DVCon Europe 2021 takes place from October 26 to 27, followed by the SystemC Evolution Day on October 28.
To read the full letter, visit here. For more information on DVCon Europe 2021, visit the conference website.
SystemC Evolution Day 2021
The sixth annual SystemC Evolution Day will be held virtually on October 28 following the virtual DVCon Europe conference. SystemC Evolution Day is intended as a lean, user-centric, hands-on forum bringing together experts from the SystemC user community and the Accellera working groups to advance SystemC standards.
For more information about SystemC Evolution Day, including past presentations and summaries, visit here. The program and free registration will be available in July.
DVCon India 2021
Save the date! DVCon India 2021 will be held on a virtual platform December 15-16. More information will be coming soon.
Additional Event Information
For more information on upcoming events throughout the year, please visit the Accellera events page. Information on each event will be updated as soon as it becomes available.
Recordings of the DVCon U.S. 2021 Accellera Day Sessions are Now Available!
Accellera sponsored several sessions from our working groups at DVCon U.S. that are now available to view and download. Sessions include a tutorial on Portable Stimulus; workshops covering UVM-SystemC randomization, the emerging SA-EDI standard, UVM-based analog verification, multi-language verification, and Functional Safety; as well as a UVM Birds-of-a-Feather.
For more information and to view or download a session, visit the Accellera Day 2021 page.
IEEE Get Program Update
Since its inception, the Accellera-sponsored IEEE Get Program has resulted in more than 125,000 downloads. The IEEE Get Program provides no cost access of electronic design and verification standards to engineers and chip designers worldwide. For more information and to view the standards available for download, visit the Available IEEE Standards page on the Accellera website.
Accellera Global Sponsors
Contact us if you interested in becoming a Global Sponsor.
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