Community Newsletter: November 2025

IN THIS ISSUE:

• Message from the Chair: Reflecting on 2025 and Looking Ahead to 2026
• Recent Press Coverage: “Boosting Design Productivity with IP-XACT”
• Interview with PSS Working Group Chair Matthew Ballance
• Events in the First Half of 2026
  • DVCon U.S.
  • DVCon China
• Recent Events Wrap-Up
  • DVCon Taiwan
  • DVCon India
  • DVCon Europe
  • SystemC Evolution Day
• More Resources
  • IEEE GET Program – Download Standards Fee Free
  • On-Demand Videos and More

 

Message from the Chair

As the year comes to a close, it’s a good time to reflect on what we’ve accomplished together as a community and look ahead to exciting opportunities on the horizon.

This year was marked by several key milestones in our mission to advance design and verification productivity. UVM-MS 1.0 was officially released, the Federated Simulation Standard Working Group published its white paper, and the SystemC Language Working Group also issued an important update to its standard.

And we’re not done yet! The Clock Domain Crossing (CDC), SystemVerilog-MSI, and SystemC-UVM standards are nearing completion of their 1.0 releases. Draft specifications for Functional Safety, SystemC-AMS, and SystemC-Synthesis are also nearly ready for public review. Each of these efforts is an important step in strengthening our global ecosystem.

An essential part of our global presence is our family of Design and Verification Conferences (DVCon) held around the world. In October, DVCon India proudly celebrated its 10th anniversary while DVCon Europe continued its tradition of engaging design competitions and a robust academic track. These conferences continue to attract new talent, fresh ideas, and growing participation. As always, the social connections fostered at each event remain a hallmark of the DVCon experience.

Across the globe, our conferences are seeing record attendance and strong financial performance, a testament to the value they bring to our community.

A heartfelt thank you to all of our volunteers. None of these achievements would be possible without each of you. Whether you contribute to our working groups or bring your expertise and enthusiasm to DVCon events, your dedication makes Accellera a vibrant organization where innovation thrives.

Looking ahead, 2026 will be a year of opportunity and growth. Together, we will continue to push boundaries, foster collaboration, and deliver standards that shape the future of design and verification. Let’s keep innovating and inspiring the next generation of engineers.

Whether it’s joining a working group, contributing to a specification, or participating in a DVCon event, your voice matters and your expertise can make a difference. Visit our website to learn more and get involved.

Wishing you a joyful holiday season and a bright beginning to 2026!

Sincerely,
Lu Dai, Accellera Systems Initiative Chair

 

Recent Press Coverage

Boosting Design Productivity with IP-XACT

By Daniel Payne for SemiWiki.com

IP-XACT, defined by IEEE 1685, is a standard that pulls together IP packaging, integration, and reuse. For anyone building modern SoCs (Systems on Chip), IP-XACT isn’t just another XML schema: it is a productivity multiplier and a risk-reduction tool that brings order to your electronic system design.

What is IP-XACT?
IP-XACT is a flexible, machine-readable format based on XML that captures the structure, interfaces, registers, and configuration of electronic components—IP blocks, subsystems, and full-chip assemblies. By describing everything from register maps and interfaces to bus protocols in a standard language, it eliminates the ambiguity and error-prone processes that have plagued chip integrations for decades.

Read the full IP-XACT article >

 

Interview with PSS Working Group Chair

Portable Stimulus (PSS) Working Group Chair, Matthew Ballance, provides some insight into PSS with two new videos. The standard continues to gain momentum with the recent release of version 3.0, delivering major advances such as runtime behavioral coverage, an expanding methodology library, and easier scenario reuse across IP, subsystem, and SoC levels. Industry adoption is growing as companies realize tangible benefits in verification efficiency and coverage. The working group is already preparing PSS 3.1, focusing on expanded modeling capabilities and ease of use. For more information, check out the videos on demand:

•  “Portable Stimulus 3.0 Brings Key Advances as Work on 3.1 Accelerates”

• “Explore the Upcoming Features in Portable Stimulus 3.1”

 

Events in the First Half of 2026

Get Ready for DVCon U.S. 2026: AI Keynotes, New Location, and Early Registration

DVCon U.S. will be held March 2-5, 2026, at its new location at the Hyatt Regency Santa Clara. There will be an industry keynote, “Designing the Future of Electronic Design with AI,” presented by Amit Gupta, senior vice president and general manager at Siemens EDA, and an invited keynote, “From Pixels to Tokens: Chip Design and Verification in the Era of AI,” presented by Stuart Oberman, vice president of GPU hardware engineering at NVIDIA.

The technical program is still being developed, but information on many of the sponsored workshops and tutorials is available on the conference website.

Early rates for DVCon U.S. 2026 registration are available through January 4, 2026.

For the latest updates and program information, visit DVCon.org.

To view sessions from past DVCon conferences, visit the DVCon Papers, Posters, Presentations and Video Archive site.

DVCon China 2026: Empowering the Next Wave of Chip Innovation

Welcome Message from the DVCon China 2026 General Chair
Dear attendees and colleagues,

Hello everyone! Welcome to the 2026 DVCon China Conference! As the chair of this conference, l am truly honored to be here with all of you. lt's exciting to gather together and discuss the latest trends and cutting-edge technologies in the field of design verification.

In recent years, we've seen tremendous growth in China's chip development across various sectors, particularly in critical areas like CPUs, GPUs, artificial intelligence, automotive electronics, communications, and the Internet of Things (loT). lt's inspiring to witness the rapid rise of domestic companies in these fields, which not only drives technological advancement but also enhances our overall market competitiveness.

As we continue to accelerate chip development, our community of design verification engineers is expanding at an impressive pace. More talented engineers are joining our ranks, bringing fresh perspectives and innovations that are vital to our industry's progress. Design verification is not just about ensuring product quality; it’s also key to improve our overall research and development efficiency.

While we strive for speed and efficiency, we must also emphasize creativity and innovation. Whether it’s through developing new tools and processes or creatively solving challenges in our engineering projects, the contributions of design verification engineers are crucial. lt's through our commitment to continuous innovation that we can stay competitive in this fast-paced market.

Every year, the DVCon China Conference attracts hundreds of engineers from leading companies across the country. This gathering is not only about learning and sharing knowledge, but it's also a fantastic opportunity to connect and network with fellow professionals. l encourage you to take advantage of this platform to explore the latest features of lC tools, discover new solutions, and make new friends in the industry. I hope after attending this conference you will leave with valuable insights that will benefit you both technically and personally.

l look forward to an enriching and exciting conference experience together!

Thank you!
Bin Liu
DVCon China 2026 General Chair

DVCon China will be held in Shanghai May 13, 2026. The Call for Abstracts is open through January 28, 2026. For more information, including topic areas and submission guidelines, visit the DVCon China website.

 

Recent Events Wrap-up

DVCon Taiwan

DVCon Taiwan 2025 wrapped up on September 9 with outstanding participation. More than 240 registered attendees and 60 participating organizations came together for a full day of technical presentations and networking with colleagues.

This year’s program delivered a rich mix of content, including three presentation tracks, two insightful keynotes, exhibition booths, and a well-received panel discussion on GenAI. The strong turnout underscored the growing momentum and influence of the design and verification community in Taiwan.

For the latest information, including upcoming conference dates, visit the DVCon Taiwan website.

DVCon India

DVCon India 2025 marked a milestone 10th anniversary celebration, bringing together a vibrant and growing community of design and verification professionals from across the region. The two-day event featured a rich blend of keynotes, technical sessions, tutorials, and panel discussions, along with an active exhibition area. Attendees benefited from in-depth presentations across multiple tracks, covering topics such as verification methodology, mixed-signal design, functional safety, AI-driven verification, and more.

A highlight of the program was the continued success of the design and verification competitions and a strong academic track, which brought together students, researchers, and industry leaders to share fresh ideas and emerging perspectives. In addition to best paper and poster awards, the conference presented awards for Lifetime Achievement, Woman Achiever in Semiconductor Industry, Design Contest, and much more. For a complete list of award recipients, visit DVCon-India.org.

Save the date! DVCon India 2026 will be held September 1-3 in Bangalore.

DVCon Europe

DVCon Europe 2025, held October 14–15 with SystemC Evolution Day on October 16, continued its strong momentum with more exhibitors, expanded tutorials, and a growing number of attendees. The conference also saw a notable increase in academic and research participation, with more papers submitted year over year. The conference and exhibition once again served as a key venue for collaboration across the design and verification community in Europe.

This year’s technical program highlighted advancements in open source, virtual prototyping, AI, automotive applications, and federated simulation. A lively panel session explored the challenges of systems-of-systems design and the need for broad, interconnected industry ecosystems.
General Chair Mark Burton noted, “DVCon Europe continues to evolve and expand, and we are particularly pleased with the growing contributions from universities and research organizations. We have also found an excellent blend with the engineering track.”

Awards were presented to recognize outstanding work across engineering and research. For a complete list of award recipients, read the full press release here.

DVCon Europe 2026 will take place in Munich on November 17–18, followed by SystemC Evolution Day on November 19, 2026.

For the most up-to-date information, visit the DVCon Europe website.

SystemC Evolution Day

Held on October 16 immediately following DVCon Europe, the 10th annual SystemC Evolution Day gathered the SystemC user community and Accellera working group members for a full-day, hands-on workshop aimed at advancing the SystemC ecosystem.
Key highlights:

• The agenda included a deep dive into SystemC 4.0 standardization (covering timeline, data types, parallel execution support, and TLM introspection).
• A special session on “What’s Next (5.0?)” collected user ideas and shaped the roadmap for future SystemC extensions.
• A presentation on federated simulation underlined cross-platform interoperability and collaborative ecosystems.
• Also included were coverage of the SystemC Summer of Code, updates from working groups, and virtual-platform case studies.

For more information on SystemC Evolution Day and other SystemC events, visit the SystemC community portal at SystemC.org.

 

More Resources

Explore Hundreds of Accellera and DVCon Videos On-Demand

Find the latest videos from our working groups, industry events and technical presentations on Accellera’s YouTube channel. We also host an extensive collection of videos on our Vimeo channel. Check out both platforms and explore content that interests you.

For more videos from our DVCon conferences, visit the DVCon Papers, Posters, Presentations and Video Archive site.

IEEE GET Program – Download Standards at No Cost

The IEEE GET Program provides engineers and chip designers worldwide with no cost access to electronic design and verification standards. For more information and to view the standards available for download, visit the Available IEC/IEEE Standards page on the Accellera website.

 

Accellera Global Sponsors

Contact us if you are interested in becoming a Global Sponsor.

 

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